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PDF HI5630 Data sheet ( Hoja de datos )
| Número de pieza | HI5630 | |
| Descripción | 80MSPS A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HI5630 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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® cN1o-On8Dt8aaR8tcE-atICNOoSOTBuhEMSreROTMeSeLtEcIELNhTnDoEirEcPwDaRlwRSOwEuD.PpiUnpLtCoAeTrrCtsEiClM.ecnEotmNeTr/tastc March 2003
HI5630
FN4645.3
Triple 8-Bit, 80MSPS A/D Converter with
Internal Voltage Reference
The HI5630 is a monolithic, triple 8-bit, 80MSPS
analog-to-digital converter fabricated in an advanced CMOS
process. It is designed for digitizing RGB graphics from work
stations and personal computers. The HI5630 reaches a
new level of multi-channel integration. The fully pipeline
architecture and an innovative input stage enable the
HI5630 to accept a variety of single-ended or fully differential
input configurations which present valid data to the output
bus with a latency of 5 clock cycles. Only one external clock
is necessary to drive all three converters with a clock out
signal provided. An internal band-gap voltage reference is
also provided allowing the system designer to realize an
increased level of system integration resulting in decreased
cost and power dissipation.
The HI5630 can be bench tested using a complete ADC
evaluation board with clock drivers, ADC, latches and a
reconstruct DAC. In addition, complete LCD monitor
reference designs are available for immediate volume
production (contact factory).
Partwww.DataSheet4U.com Number Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
PKG. NO.
HI5630/8CN
0 to 70 64 Ld MQFP
Q64.14x14
HI5630EVAL1
25 ADC Evaluation Platform
Features
• Triple 8-Bit A/D Converter on a Monolithic Chip
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 80MSPS
• ENOB (fIN = 1MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6
• Wide Full Power Input Bandwidth . . . . . . . . . . . . 300MHz
• Internal Band-Gap Voltage Reference . . . . . . . . . . . . 2.5V
• Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB
• Single Supply Voltage Operation . . . . . . . . . . . . . . . . .+5V
• On-Chip Sample and Hold Amplifiers
• Clock Output
• Offset Binary or Two’s Complement Output Format
• Stand-By Low Power mode
Applications
• LCD Monitors, Projectors and Plasma Display Panels
• Video Digitizing (RGB, Composite or Y-C)
• Medical Imaging
• High Speed Multi-Channel Data Acquisition
Pinout
HI5630
(MQFP)
TOP VIEW
DGND
DVDD
GD1
GD2
GD3
DGND
DVDD
CLKOUT
CLKIN
DVDD
DGND
GD4
GD5
GD6
DVDD
DGND
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AGND
BIN +
BIN -
BVDC
AGND
VRIN
VROUT
AVDD
GIN +
GIN -
GVDC
AGND
AVDD
RIN +
RIN -
RVDC
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
HI5630
Absolute Maximum Ratings TA = 25oC
Supply Voltage, AVDD or DVDD to AGND or DGND . . . . . . . . . . .6V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVDD
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVDD
Operating Conditions
Temperature Range
HI5630/8CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
MQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a 1S2P (1 Signal and 2 Power) evaluation PC board in free air.
Electrical Specifications
ATAVD=D25=o5CV;,UDnVleDsDs
= 5V; Single Ended Inputs,
Otherwise Specified
VRIN
=
2.5V;
fS
=
80MSPS
at
50%
Duty
Cycle;
CL
=
10pF;
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
ACCURACY
Resolution
- 8 - Bits
Integral Linearity Error, INL
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
fIN = 1MHz
fIN = 1MHz
-
±0.4 ±2.0
LSB
-
±0.2 ±1.0
LSB
Channel Offset Match
Channel Full Scale Error Match
Offset Code, VOC
Full Scale Error, FSE
Bit Error Rate (BER)
fIN = DC
fIN = DC
VIN+ = VIN-
fIN = DC
- 1 - LSB
- 0.25 -
LSB
- 140 - CODE
- 1 - LSB
---
s
ANALOG INPUT
Analog Input Range
(Note 2)
- 0.95 1
V
Analog Input Resistance
Analog Input Capacitance
VIN+ = VIN- = VREF
- 1 - MΩ
- 10 -
pF
Analog Input Bias Current
Full Power Input Bandwidth, FPBW
VIN+ = VIN- = VREF
-10 1.0 10
- 300 -
µA
MHz
INTERNAL VOLTAGE REFERENCE 1µF Decoupling Cap Needed
Reference Output Voltage, VREF
Reference Output Current, IROUT
Reference Temperature Coefficient
IREF = 4mA
V Applied = 2.5V
2.33 2.5 2.67
V
- 2 4 mA
- 6 - µV/oC
DC BIAS PINS RVDC, GVDC, BVDC with 0.1µF Decoupling Cap Needed
VDC Output Voltage (Loaded)
- 1.97 -
V
VDC Output Current, IVDC
VDC Temperature Coefficient
- - - mA
- 60 - µV/oC
REFERENCE VOLTAGE INPUT
Reference Voltage Input, VRIN
Total Reference Resistance, RRIN
Reference Current, IRIN
DYNAMIC CHARACTERISTICS
(Note 2)
VRIN = 2.5V
VRIN = 2.5V
2.2 2.5 2.8
- 2.93 -
- 0.95 -
V
kΩ
mA
Minimum Conversion Rate
No Missing Codes
1 - - MSPS
Maximum Conversion Rate
No Missing Codes
- - 80 MSPS
Overclocking Conversion Rate
No Missing Codes
- 95 - MSPS
Transient Response
- 1 - Cycle
5
5 Page 
HI5630
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI5630. A low
distortion sine wave is applied to the input, it is coherently
sampled, and the output is stored in RAM. The data is then
transformed into the frequency domain with an FFT and
analyzed to evaluate the dynamic performance of the A/D.
The sine wave input to the part is typically -0.5dB down from
full scale for all these tests.
SNR and SINAD are quoted in dB. The distortion numbers
are quoted in dBc (decibels with respect to carrier) and DO
NOT include any correction factors for normalizing to full scale.
The Effective Number of Bits (ENOB) is calculated from the
SINAD data by:
ENOB = (SINAD - 1.76 + VCORR) / 6.02,
where: VCORR = 0.5dB (Typical).
VCORR adjusts the SINAD, and hence the ENOB, for the
amount the analog input signal is backed off from full scale.
Signal To Noise and Distortion Ratio (SINAD) - SINAD is
the ratio of the measured RMS signal to RMS sum of all the
other spectral components below the Nyquist frequency,
fS/2, excluding DC.
Signal To Noise Ratio (SNR) - SNR is the ratio of the
measured RMS signal to RMS noise at a specified input and
sampling frequency. The noise is the RMS sum of all of the
spectral components below fS/2 excluding the fundamental,
the first five harmonics and DC.
Total Harmonic Distortion (THD) - THD is the ratio of the
RMS sum of the first 5 harmonic components to the RMS
value of the fundamental input signal.
2nd and 3rd Harmonic Distortion - This is the ratio of the
RMS value of the applicable harmonic component to the
RMS value of the fundamental input signal.
Spurious Free Dynamic Range (SFDR) - SFDR is the ratio
of the fundamental RMS amplitude to the RMS amplitude of the
next largest spectral component in the spectrum below fS/2.
Intermodulation Distortion (IMD) - Nonlinearities in the
signal path will tend to generate intermodulation products
when two tones, f1 and f2, are present at the inputs. The
ratio of the measured signal to the distortion terms is
calculated. The terms included in the calculation are (f1+f2),
(f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2), (f1+2f2), (f1-2f2). The
ADC is tested with each tone 6dB below full scale.
Transient Response - Transient response is measured by
providing a full-scale transition to the analog input of the
ADC and measuring the number of cycles it takes for the
output code to settle within 8-bit accuracy.
Over-Voltage Recovery - Over-Voltage Recovery is
measured by providing a full-scale transition to the analog
input of the ADC which overdrives the input by 200mV, and
measuring the number of cycles it takes for the output code
to settle within 8-bit accuracy.
Full Power Input Bandwidth (FPBW) - Full power input
bandwidth is the analog input frequency at which the
amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has an amplitude which swings from
-FS to +FS. The bandwidth given is measured at the
specified sampling frequency.
Video Definitions
Differential Gain and Differential Phase are two commonly
found video specifications for characterizing the distortion of
a chrominance signal as it is offset through the input voltage
range of an ADC.
Differential Gain (DG) - Differential Gain is the peak
difference in chrominance amplitude (in percent) relative to
the reference burst.
Differential Phase (DP) - Differential Phase is the peak
difference in chrominance phase (in degrees) relative to the
reference burst.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (tAP) - Aperture delay is the time delay
between the external sample command (the falling edge of
the clock) and the time at which the signal is actually sampled.
This delay is due to internal clock path propagation delays.
Aperture Jitter (tAJ) - Aperture jitter is the RMS variation in
the aperture delay due to variation of internal clock path delays.
Data Hold Time (tH) - Data hold time is the time to where
the previous data (N - 1) is no longer valid.
Data Output Delay Time (tOD) - Data output delay time is
the time from the rising edge of the external sample clock to
where the new data (N) is valid.
Data Latency (tLAT) - After the analog sample is taken, the
digital data representing an analog input sample is output to
the digital data bus on the 7th cycle of the clock after the
analog sample is taken. This is due to the pipeline nature of
the converter where the analog sample has to ripple through
the internal subconverter stages. This delay is specified as
the data latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital data lags the
analog input sample by 7 sample clock cycles.
Power-Up Initialization - This time is defined as the
maximum number of clock cycles that are required to
initialize the converter at power-up. The requirement arises
from the need to initialize the dynamic circuits within the
converter.
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HI5630.PDF ] | |
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