PDF HI5634 Data sheet ( Hoja de datos )

Número de pieza	HI5634
Descripción	High Performance Programmable Phase-Locked Loop
Fabricantes	Intersil Corporation
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No Preview Available ! PRELIMINARY Data Sheet HI5634 May 1999 File Number 4745 High Performance Programmable Phase-Locked Loop for LCD Applications The HI5634 is a low cost but very high-performance frequency generator for line-locked and genlocked high resolution video applications. Utilizing an advanced low voltage CMOS mixed signal technology, the HI5634 is an effective clock solution for video projectors and displays at resolutions from VGA to beyond UXGA The HI5634 offers pixel clock outputs in both differential (to 250MHz) and single-ended (to 150MHz) formats. Digital phase adjustment circuitry allows user control of the pixel clock phase relative to the recovered sync signal. A second differential output at half the pixel clock rate enables deMUXing of multiplexed A/D converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output or a re-synchronized and sharpened input HSYNC. The advanced PLL utilizes either its internal programmable feedback divider or an external divider. The device is programmed by a standard I2C-bus® serial interface. Simpliﬁed Block Diagram www.DataSheet4U.com LOOP FILTER OSC HSYNC I2C INTERFACE PHASE LOCKED LOOP DIGITAL PHASE ADJUST CLK CLK/2 FUNC Ordering Information TEMP. PART NUMBER RANGE (oC) PACKAGE HI5634CB 0 to 70 24 Ld SOIC PKG. NO. M24.3 Features • Pixel Clock Frequencies up to 250MHz • Very Low Jitter • Digital Phase Adjustment (DPA) for Clock Outputs • Balanced PECL Differential Outputs • Single-Ended SSTL_3 Clock Outputs • Double-Buffered PLL/DPA Control Registers • Independent Software Reset for PLL/DPA • External or Internal Loop Filter Selection • Uses 3.3V Supply. Inputs are 5V Tolerant. • I2C-bus Serial Interface can Run at Either Low Speed (100kHz) or High Speed (400kHz) • Lock Detection Applications • LCD Monitors and Video Projectors • Genlocking Multiple Video Subsystems • Frequency Synthesis Pinout HI5634 (SOIC) TOP VIEW VDDD 1 VSSD 2 SDA 3 SCL 4 PDEN 5 EXTFB 6 HSYNC 7 EXTFIL 8 EXTFILRET 9 VDDA 10 VSSA 11 OSC 12 24 IREF 23 CLK/2+ (PECL) 22 CLK/2- (PECL) 21 CLK+ (PECL) 20 CLK- (PECL) 19 VSSQ 18 VDDQ 17 CLK (SSTL) 16 CLK/2 (SSTL) 15 FUNC (SSTL) 14 LOCK/REF (SSTL) 13 I2CADR 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 I2C Bus is a Trademark of Philips Corporation. 1 page HI5634 Electrical Speciﬁcations Per Operating Conditions Listed Above, Unless Otherwise Speciﬁed (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PECL Clock Duty Cycle t2, t3 45 50 55 % PECL Clock to SSTL Clock Delay t4 0.2 0.75 1.2 ns PECL Clock to FUNC Delay t5 1.5 1.9 2.3 ns PECL Clock to PECL Clock/2 Delay t6 1.0 1.3 1.5 ns PECL Clock to SSTL Clock/2 Delay t7 1.1 1.4 1.8 ns SSTL Clock Duty Cycle t8, t9 45 50 55 % NOTES: 4. VOL must not fall below the minimum specified level or the IOUT value may not be maintained. 5. Measured at 3.6V 0oC, 135MHz output frequency, PECL Clock lines to 75Ω termination, SSTL Clock lines unterminated, 20pF load. Transition times vary based on termination. See the “Output Timing Diagram” for details. Application Information Overview The HI5634 addresses stringent graphics system line locked and genlocked applications and provides the clock signals required by high-performance video A/D converters. Included are a phase locked loop (PLL) with a 500MHz voltage controlled oscillator (VCO), a digital phase adjustment to provide a user programmed pixel clock delay, the means for deMUXing multiplexed A/D Converters, and both balanced programmable (PECL) and single-ended (SSTL_3) high-speed clock outputs. Phase-Locked Loop The phase-locked loop is optimized for line-locked applications, for which the inputs are horizontal sync signals. A high-performance Schmitt trigger preconditions the HSYNC input, whose pulses can be degraded if they are from a remote source. This preconditioned HSYNC signal is provided as a clean reference signal with a short transition time (in contrast, the signal that a typical PC graphics card provides has a transition time of tens of nanoseconds). A second high frequency input such as a crystal oscillator and a 7-bit programmable divider can be selected. This selection allows the loop to operate from a local source and is also useful for evaluating intrinsic jitter. A 12-bit programmable feedback divider completes the loop. Designers can substitute an external divider. Either the conditioned HSYNC input or the loop output (recovered HSYNC) is available at the FUNC pin, aligned to the edge of the pixel clock. Automatic Power-On-Reset Detection The HI5634 has automatic power-on-reset detection circuitry and it resets itself if the supply voltage drops below threshold values. No external connection to a reset signal is required. Digital Phase Adjustment The digital phase adjustment allows addition of a programmable delay to the pixel clock output, relative to the recovered HSYNC signal. The ability to add delays is particularly useful when multiple video sources must be synchronized. A delay of up to one pixel clock period is selectable in the following increments: 1/64 period for pixel clock rates to 40MHz 1/32 period for pixel clock rates to 80MHz 1/16 period for pixel clock rates to 160MHz Output Drivers and Logic Inputs The HI5634 utilizes low voltage TTL (LVTTL) inputs as well as SSTL_3 (EIA/JESD8-8) and low voltage PECL (pseudo- ECL) outputs, operating at 3.3V supply voltage. The LVTTL inputs are 5V tolerant. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated unterminated. I 2C-bus Serial Interface The HI5634 utilizes the industry standard I2C-bus serial interface. The interface uses 12 registers: one write-only, eight read/write, and three read-only. Two HI5634 devices can be addressed, according to the state of the I2 CADR pin. When the pin is low, the read address is 4Dh, and the write address is 4Ch. When the pin is high, the read address is 4Fh, and the write address is 4Eh. The I2C-bus serial interface can run at either low speed (100kHz) or high speed (400kHz) and provides 5V tolerant input. PC Board Layout Use a PC board with at least four layers: one power, one ground, and two signal. No special cutouts are required for power and ground planes. All supply voltages must be supplied from a common source and must ramp up together. Flux and other board surface debris can degrade the performance of the external loop ﬁlter. Ensure that the HI5634 area of the board is free of contaminants. 5 5 Page HI5634 Register: 6h BIT NAME BIT # OE_PCK 0 OE_TCK 1 OE_P2 2 OE_T2 3 OE_F 4 CK2_INV 5 OUT_SCL 6-7 Name: Output Enable Register Access: Read/Write RESET VALUE DESCRIPTION 0 Output Enable for CLK Outputs (PECL) - 0 = High Z (default), 1 = Enabled. 0 Output Enable for CLK Output (SSTL_3) - 0 = High Z (default), 1 = Enabled. 0 Output Enable for CLK/2 Outputs (PECL) - 0 = High Z (default), 1 = Enabled. 0 Output Enable for CLK/2 Output (SSTL_3) - 0 = High Z (default), 1 = Enabled. 0 Output Enable for FUNC Output (SSTL_3) - 0 = High Z (default), 1 = Enabled. 0 CLK/2 Invert - 0 = Not Inverted (default), 1 = Inverted. 0 Clock (CLK) Scaler. BIT 7 BIT 6 00 01 10 11 CLK DIVIDER 1 2 4 8 Register: 7h Name: Oscillator Divider Register Access: Read/Write BIT NAME BIT # RESET VALUE DESCRIPTION OSC_DIV0- 6 0-6 0 Oscillator Divider Modulus - Divides the input from OSC (pin 12) by the set modulus. The modulus equals the programmed value, plus 2. Therefore, the modulus range is from 3 to 129. IN_SEL 7 1 Input Select - Selects the input to the Phase/Frequency Detector 0 = HSYNC, 1 = Osc Divider (default). Register: 8h Name: Reset Register Access: Write Only BIT NAME BIT # RESET VALUE DESCRIPTION DPA Reset 0-3 X Writing XAh to this register resets DPA working Register 5. PLL Reset 4-7 X Writing 5Xh to this register resets PLL working Registers 1-3. VALUE XA 5X 5A RESETS DPA PLL DPA and PLL Register: 10h Name: Chip Version Register BIT NAME BIT # RESET VALUE CHIP VER 0-7 17 Chip Version 23 (17h). Access: Read Only DESCRIPTION Register: 11h Name: Chip Revision Register Access: Read Only BIT NAME BIT # RESET VALUE DESCRIPTION CHIP REV 0-7 01+ Initial value 01h. +Value increments with each all-layer change. Register: 12h Name: Status Register Access: Read Only BIT NAME BIT # RESET VALUE DESCRIPTION DPA_LOCK 0 N/A DPA Lock Status (Refer to Register 0h, bits 6 and 7). 0 = Unlocked, 1 = Locked. PLL_LOCK 1 N/A PLL Lock Status (Refer to Register 0h, bits 6 and 7). 0 = Unlocked, 1 = Locked. Reserved 2-7 0 Reserved 11 11 Page

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