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PDF USB3500 Data sheet ( Hoja de datos )

Número de pieza USB3500
Descripción Hi-Speed USB Host
Fabricantes SMSC Corporation　
Logotipo SMSC Corporation Logotipo



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USB3500
Hi-Speed USB Host,
Device or OTG PHY
With UTMI+ Interface
PRODUCT FEATURES
■ USB-IF “Hi-Speed” certified to the Universal Serial
Bus Specification Rev 2.0
■ Interface compliant with the UTMI+ Specification,
Revision 1.0.
■ Includes full support for the optional On-The-Go
(OTG) protocol detailed in the On-The-Go
Supplement Revision 1.0a specification.
■ Functional as a host, device or OTG PHY.
■ Supports HS, FS, and LS data rates.
■ Supports FS pre-amble for FS hubs with a LS device
attached (UTMI+ Level 3)
■ Supports HS SOF and LS keep alive pulse.
■ Supports Host Negotiation Protocol (HNP) and
Session Request protocol (SRP.)
■ Internal comparators support OTG monitoring of
VBUS levels.
■ Low Latency Hi-Speed Receiver (43 Hi-Speed clocks
Max)
Datasheet
■ Internal 1.8 volt regulators allow operation from a
single 3.3 volt supply
■ Internal short circuit protection of ID, DP and DM
lines to VBUS or ground.
■ Integrated 24MHz Crystal Oscillator supports either
crystal operation or 24MHz external clock input.
■ Internal PLL for 480MHz Hi-Speed USB operation.
■ Supports USB2.0 and legacy USB 1.1 devices
■ 55mA Unconfigured Current (typical) - ideal for bus
powered applications.
■ 83uA suspend current (typical) - ideal for battery
powered applications.
■ Full Commercial operating temperature range from
0C to +70C
■ 56 Pin QFN package; green, lead-free (8 x 8 x 0.90
mm height)
SMSC USB3500
DATASHEET
Revision 1.0 (04-04-05)

1 page




USB3500 pdf
Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface
Datasheet
List of Figures
Figure 1.1 Basic UTMI+ USB Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 1.2 UTMI+ Level 3 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2.1 USB3500 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3.1 USB3500 Pinout - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6.1 FS CLK Relationship to Transmit Data and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6.2 FS CLK Relationship to Receive Data and Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6.3 Transmit Timing for a Data Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6.4 Receive Timing for Data with Unstuffed Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 6.5 Receive Timing for a Handshake Packet (no CRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6.6 Receive Timing for Setup Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6.7 Receive Timing for Data Packet (with CRC-16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6.8 USB3500 On-the-Go Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 7.1 Reset Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 7.2 Suspend Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 7.3 HS Detection Handshake Timing Behavior (FS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 7.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 7.5 HS Detection Handshake Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 7.6 HS Detection Handshake Timing Behavior from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 7.7 Resume Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 7.8 Device Attach Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 7.9 USB Reset and Chirp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 7.10 USB3500 Application Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 8.1 USB3500-ABZJ 56 Pin QFN Package Outline, 8 x 8 x 0.9 mm Body (Lead Free) . . . . . . . . 46
SMSC USB3500
5
DATASHEET
Revision 1.0 (04-04-05)

5 Page





USB3500 arduino
Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface
Datasheet
3.2 Pin Definitions
PIN NAME
1 VSS
2 XCVRSEL[0]
3 TERMSEL
4 TXREADY
5 VBUS
6 ID
7 SUSPENDN
8 TXVALID
9 RESET
10 VDD3.3
11 DP
SMSC USB3500
Table 3.1 USB3500 Pin Definitions
DIRECTION, ACTIVE
TYPE
LEVEL DESCRIPTION
Ground
Input
Input
Output
I/O,
Analog
Input,
Analog
Input
Input
Input
N/A
I/O,
Analog
N/A
N/A
N/A
High
N/A
PHY ground.
Transceiver Select. These signals select between
the FS and HS transceivers:
Transceiver select.
00: HS
01: FS
10: LS
11: LS data, FS rise/fall times
Termination Select. This signal selects between the
FS and HS terminations:
0: HS termination enabled
1: FS termination enabled
Transmit Data Ready. If TXVALID is asserted, the
Link must always have data available for clocking
into the TX Holding Register on the rising edge of
CLKOUT. TXREADY is an acknowledgement to the
Link that the transceiver has clocked the data from
the bus and is ready for the next transfer on the bus.
If TXVALID is negated, TXREADY can be ignored by
the Link.
VBUS pin of the USB cable.
N/A ID pin of the USB cable.
Low
High
High
N/A
N/A
Suspend. Places the transceiver in a mode that
draws minimal power from supplies. In host mode,
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0: PHY in suspend mode
1: PHY in normal operation
Transmit Valid. Indicates that the DATA bus is valid
for transmit. The assertion of TXVALID initiates the
transmission of SYNC on the USB bus. The
negation of TXVALID initiates EOP on the USB.
Control inputs (OPMODE[1:0],
TERMSEL,XCVERSEL) must not be changed on the
de-assertion or assertion of TXVALID.
Reset. Reset all state machines. After coming out
of reset, must wait 5 rising edges of clock before
asserting TXValid for transmit.
Assertion of Reset: May be asynchronous to
CLKOUT
De-assertion of Reset: Must be synchronous to
CLKOUT
3.3V PHY Supply. Provides power for USB2.0
Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.
D+ pin of the USB cable.
11
DATASHEET
Revision 1.0 (04-04-05)

11 Page







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