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PDF USB3300 Data sheet ( Hoja de datos )
| Número de pieza | USB3300 | |
| Descripción | Hi-Speed USB Host | |
| Fabricantes | SMSC Corporation | |
| Logotipo |  |
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USB3300
Hi-Speed USB Host,
Device or OTG PHY with
ULPI Low Pin Interface
PRODUCT FEATURES
USB-IF Hi-Speed certified to the Universal Serial Bus
Specification Rev 2.0
Interface compliant with the ULPI Specification
revision 1.1 in 8-bit mode
Industry standard UTMI+ Low Pin Interface (ULPI)
Converts 54 UTMI+ signals into a standard 12 pin
Link controller interface
54.7mA Unconfigured Current (typical) - ideal for bus
powered applications
83uA suspend current (typical) - ideal for battery
powered applications
Latch-Up performance exceeds 150 mA per
EIA/JESD 78, Class II
ESD protection levels of ±8kV HBM without external
protection devices
Integrated protection to withstand IEC61000-4-2 ESD
tests (±8kV contact and ±15kV air) per 3rd party test
facility
Supports FS pre-amble for FS hubs with a LS device
attached (UTMI+ Level 3)
Supports HS SOF and LS keep-alive pulse
Includes full support for the optional On-The-Go
(OTG) protocol detailed in the On-The-Go
Supplement Revision 1.0a specification
Supports the OTG Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
Allows host to turn VBUS off to conserve battery
power in OTG applications
Supports OTG monitoring of VBUS levels with
internal comparators. Includes support for an external
VBUS or fault monitor.
Datasheet
Low Latency Hi-Speed Receiver (43 Hi-Speed clocks
Max) allows use of legacy UTMI Links with a ULPI
wrapper
Integrated Pull-up resistor on STP for interface
protection allows a reliable Link/PHY start-up with
slow Links (software configured for low power)
Internal 1.8 volt regulators allow operation from a
single 3.3 volt supply
Internal short circuit protection of ID, DP and DM
lines to VBUS or ground
Integrated 24MHz Crystal Oscillator supports either
crystal operation or 24MHz external clock input
Internal PLL for 480MHz Hi-Speed USB operation
Industrial Operating Temperature -40°C to +85°C
32 pin QFN package; green, lead-free (5 x 5 x 0.90
mm height)
APPLICATIONS
The USB3300 is the ideal companion to any ASIC, SoC
or FPGA solution designed with a ULPI Hi-Speed USB
host, peripheral or OTG core.
The USB3300 is well suited for:
Cell Phones
PDAs
MP3 Players
Scanners
External Hard Drives
Digital Still and Video Cameras
Portable Media Players
Printers
SMSC USB3300
DATASHEET
Revision 1.06 (07-19-06)
1 page  
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
Datasheet
List of Figures
Figure 1.1 Basic ULPI USB Device Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 1.2 ULPI Interface Features as Related to UTMI+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2.1 USB3300 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3.1 USB3300 Pin Diagram - Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6.1 Simplified USB3300 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6.2 ULPI Digital Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6.3 ULPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6.4 ULPI Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 6.5 ULPI Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 6.6 ULPI Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 6.7 ULPI Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 6.8 Entering Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 6.9 Exiting Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 6.10 USB3300 On-the-Go Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 7.1 USB3300 Application Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7.2 Expanding Downstream Ports for USB3300 Host Applications . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 8.1 USB3300-EZK 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free) . . . . . . . . . 49
SMSC USB3300
5
DATASHEET
Revision 1.06 (07-19-06)
5 Page 
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
Datasheet
Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package (continued)
DIRECTION, ACTIVE
PIN NAME
TYPE
LEVEL DESCRIPTION
4 VBUS
I/O,
Analog
N/A VBUS pin of the USB cable. The USB3300 uses this
pin for the Vbus comparator inputs and for Vbus
pulsing during session request protocol.
5 ID
6 VDD3.3
7 DP
Input,
Analog
Power
I/O,
Analog
N/A ID pin of the USB cable. For non-OTG applications
this pin can be floated. For an A-Device ID = 0. For
a B-Device ID = 1.
N/A 3.3V Supply. A 0.1uF bypass capacitor should be
connected between this pin and the ground plane on
the PCB.
N/A D+ pin of the USB cable.
8 DM
I/O,
Analog
N/A D- pin of the USB cable.
9
RESET
Input, CMOS High Optional active high transceiver reset. This is the
same as a write to the ULPI Reset, address 04h, bit
5. This does not reset the ULPI register set. This
signal must be de-asserted synchronous to
CLKOUT. This pin includes an integrated pull-down
resistor to ground. If not used this pin can be floated
or connected to ground (recommended).
10
EXTVBUS
Input, CMOS High External Vbus Detect. Connect to fault output of an
external USB power switch or an external Vbus Valid
comparator. See Section 6.5.4, "External Vbus
Indicator," on page 44 for details. This pin has a pull
down resistor to prevent it from floating when the
ULPI bit UseExternalVbusIndicator is set to 0.
11 NXT
Output,
CMOS
High
The PHY asserts NXT to throttle the data. When the
Link is sending data to the PHY, NXT indicates when
the current byte has been accepted by the PHY. The
Link places the next byte on the data bus in the
following clock cycle.
12 DIR
Output,
CMOS
N/A Controls the direction of the data bus. When the
PHY has data to transfer to the Link, it drives DIR
high to take ownership of the bus. When the PHY
has no data to transfer it drives DIR low and
monitors the bus for commands from the Link. The
PHY will pull DIR high whenever the interface cannot
accept data from the Link, such as during PLL start-
up.
13 STP
14 CLKOUT
15 VDD1.8
16 VDD3.3
Input,
CMOS
Output,
CMOS
Power
Power
High
N/A
N/A
N/A
The Link asserts STP for one clock cycle to stop the
data stream currently on the bus. If the Link is
sending data to the PHY, STP indicates the last byte
of data was on the bus in the previous cycle. The
STP pin also includes the interface protection
detailed in Section 6.1.9.3, "Interface Protection," on
page 36.
60MHz reference clock output. All ULPI signals are
driven synchronous to the rising edge of this clock.
1.8V regulator output for digital circuitry on chip.
Place a 0.1uF capacitor near this pin and connect
the capacitor from this pin to ground. Connect pin 15
to pin 26.
A 0.1uF bypass capacitor should be connected
between this pin and the ground plane on the PCB.
SMSC USB3300
11
DATASHEET
Revision 1.06 (07-19-06)
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet USB3300.PDF ] | |
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