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HI5905 の電気的特性と機能

HI5905のメーカーはIntersil Corporationです、この部品の機能は「A/D Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 HI5905
部品説明 A/D Converter
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HI5905 Datasheet, HI5905 PDF,ピン配置, 機能
® cN1o-On8t8aR8DcE-atICNOtoaOTBuEMSrSROThMSeLeEcIEeLNhtTnDoEirEcPwDaRlwRSOwEuD.PpiUnpLtCoAeTrrCtsEiClM.ecnEotmNeTr/tastc
March 2003
HI5905
FN4259.4
14-Bit, 5MSPS A/D Converter
The HI5905 is a monolithic, 14-bit, 5MSPS Analog-to-
Digital Converter fabricated in an advanced BiCMOS
process. It is designed for high speed, high resolution
applications where wide bandwidth, low power
consumption and excellent SINAD performance are
essential. With a 100MHz full power input bandwidth and
high frequency accuracy, the converter is ideal for many
types of communication systems employing digital IF
architectures.
The HI5905 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold amplifier (S/H). The HI5905 has excellent
dynamic performance while consuming 350mW power at
5MSPS.
Data output latches are provided which present valid data to
the output bus with a low data latency of 4 clock cycles.
Part Number Information
PART
TEMP. RANGE
NUMBER (oC) PACKAGE
PKG.
NO.
HI5905IN
-40 to 85 44 Ld MQFP Q44.10x10
HI5905EVAL2
25 Low Frequency Eval Platform
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MSPS
• Low Power at 5MSPS . . . . . . . . . . . . . . . . . . . . . .350mW
• Internal Sample and Hold
• Fully Differential Architecture
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz
• SINAD at 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . >70dB
• Low Data Latency
• Internal Voltage Reference
• TTL Compatible Clock Input
• CMOS Compatible Digital Data Outputs
Applications
• Digital Communication Systems
• Undersampling Digital IF
• Asymmetric Digital Subscriber Line (ADSL)
• Document Scanners
• Reference Literature
- AN9214, Using Intersil High Speed A/D Converters
- AN9785, Using the Intersil HI5905 EVAL2 Evaluation
Board
Pinout
HI5905 (MQFP)
TOP VIEW
NC
NC
DGND1
NC
AVCC
AGND
NC
NC
VIN+
VIN-
VDC
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
D3
D4
D5
D6
D7
NC
DVCC2
DGND2
D8
D9
NC
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





HI5905 pdf, ピン配列
HI5905
Absolute Maximum Ratings
Supply Voltage, AVCC or DVCC to AGND or DGND. . . . . . . . . +6.0V
DGND to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND to DVCC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Operating Conditions
Temperature Range (HI5905IN) . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(MQFP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
ATAVC=C25=oDCV, CDCiff1e=reDntViaCl CA2na=lo+g5.I0nVp,uftS, U=n5leMssSPOSthaetrw50is%e
Duty Cycle,
Specified
VRIN
=
VROUT ,
CL
=
15pF,
PARAMETER
TEST CONDITIONS
MIN TYP MAX
ACCURACY
Resolution
14 -
-
Integral Linearity Error, INL
Sinewave Histogram
- ±2.5 -
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
Sinewave Histogram
-1 ±0.5 +1.5
Offset Error, VOS
Full Scale Error, FSE
DYNAMIC CHARACTERISTICS
fIN = DC
fIN = DC
- - 120
- - 164
Minimum Conversion Rate
No Missing Codes (Note 2)
-
- 0.5
Maximum Conversion Rate
No Missing Codes
5- -
Effective Number of Bits, ENOB
Signal to Noise and Distortion Ratio, SINAD
fIN = 1MHz
fIN = 1MHz
11.2 11.7
69 72.2
-
-
= ----------------R----M-----S------S----i-g----n---a---l---------------
RMS Noise + Distortion
Signal to Noise Ratio, SNR
fIN = 1MHz
71 74.6
-
=
R-----M-----S------S----i-g---n----a---l
RMS Noise
Total Harmonic Distortion, THD
2nd Harmonic Distortion
3rd Harmonic Distortion
Spurious Free Dynamic Range, SFDR
Intermodulation Distortion, IMD
Transient Response
fIN = 1MHz
fIN = 1MHz
fIN = 1MHz
fIN = 1MHz
f1 = 1MHz, f2 = 1.02MHz
-73 75.7
- -95
- -77
80 -
- 74
-1
-
-
-
-
-
Over-Voltage Recovery
0.2V Overdrive
-2-
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input Range (VIN+
- VIN-)
Maximum Peak-to-Peak Single-Ended Analog Input Range
- ±2.0 -
- 4.0 -
Analog Input Resistance, RIN
Analog Input Capacitance, CIN
Analog Input Bias Current, IB+ or IB-
Differential Analog Input Bias Current IB DIFF = (IB+ - IB-)
(Notes 1, 2)
(Note 2)
(Note 3)
1- -
- 10 16
-50 - +50
- ±0.5 -
UNITS
Bits
LSB
LSB
LSB
LSB
MSPS
MSPS
Bits
dB
dB
dBc
dBc
dBc
dBc
dBc
Cycle
Cycle
V
V
M
pF
µA
µA
3


3Pages


HI5905 電子部品, 半導体
HI5905
Typical Performance Curves
12 74
11.75
11.5
11.25
11
fIN = 1MHz
TA = 25oC
71
68
10.75
10.5
65
10.25
10 62
0 1 2 3 4 5 6 78
fS (MSPS)
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) AND
SINAD vs SAMPLE CLOCK FREQUENCY
74
fIN = 1MHz
73 TA = 25oC
72
71
70
69
68
67
66
012345678
fS (MSPS)
FIGURE 4. SNR vs SAMPLE CLOCK FREQUENCY
88
86
84
82
fIN = 1MHz
TA = 25oC
80
-2HD
78
76
-THD
74
-3HD
72
70
68
012345678
fS (MSPS)
FIGURE 5. -2HD, -3HD AND -THD vs SAMPLE CLOCK
FREQUENCY
90
fIN = 1MHz
88 TA = 25oC
86
84
82
80
78
76
012345678
fS (MSPS)
FIGURE 6. SFDR vs SAMPLE CLOCK FREQUENCY
80
fIN = 1MHz
70 TA = 25oC
60
50
AICC
ICC
40
30
DICC1 + DICC2
20
10
012345678
fS (MSPS)
FIGURE 7. SUPPLY CURRENT vs SAMPLE CLOCK FREQUENCY
6

6 Page



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共有リンク

Link :


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A/D Converter

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