|
|
PDF HI5766 Data sheet ( Hoja de datos )
| Número de pieza | HI5766 | |
| Descripción | A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HI5766 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
Data Sheet
10-Bit, 60 MSPS A/D Converter
The HI5766 is a monolithic, 10-bit, analog-to-digital
converter fabricated in a CMOS process. It is designed for
high speed applications where wide bandwidth and low
power consumption are essential. Its 60 MSPS speed is
made possible by a fully differential pipelined architecture
with an internal sample and hold.
The HI5766 has excellent dynamic performance while
consuming only 260mW power at 60 MSPS. Data output
latches are provided which present valid data to the output
bus with a latency of 7 clock cycles. It is pin-for-pin
functionally compatible with the HI5702, HI5703 and the
HI5746.
For internal voltage reference, please refer to the HI5767
data sheet.
Ordering Information
PART
NUMBER
TEMP.
RANGE (oC)
PACKAGE
HI5766KCB
0 to 70 28 Ld SOIC (W)
www.DataSheet4U.comHI5766KCA
0 to 70 28 Ld SSOP
HI5766EVAL1
25 Evaluation Board
PKG.
NO.
M28.3
M28.15
HI5766
February 1999
File Number 4130.5
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 60 MSPS
• 8.3 Bits at fIN = 10MHz
• Low Power at 60 MSPS . . . . . . . . . . . . . . . . . . . . 260mW
• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz
• On Chip Sample and Hold
• Fully Differential or Single-Ended Analog Input
• Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . +5V
• TTL/CMOS Compatible Digital Inputs
• CMOS Compatible Digital Outputs . . . . . . . . . . . . 3.0/5.0V
• Offset Binary or Two’s Complement Output Format
Applications
• Professional Video Digitizing
• Medical Imaging
• Digital Communication Systems
• High Speed Data Acquisition
Pinout
HI5766
(SOIC, SSOP)
TOP VIEW
DVCC1 1
DGND 2
DVCC1 3
DGND 4
AVCC 5
AGND 6
VREF+ 7
VREF- 8
VIN+ 9
VIN- 10
VDC 11
AGND 12
AVCC 13
OE 14
28 D0
27 D1
26 D2
25 D3
24 D4
23 DVCC2
22 CLK
21 DGND
20 D5
19 D6
18 D7
17 D8
16 D9
15 DFS
31 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1 page  
HI5766
Electrical Specifications
ACVLC=C1=0pDFV; CTCA1==255.o0CV;,
DVCC2 = 3.0V; VREF+ =
Differential Analog Input;
2.5V; VREF - =
Typical Values
2.0V; fS
are Test
= 60 MSPS at 50%
Results at 25oC,
Duty
Cycle;
Unless Otherwise Specified (Continued)
PARAMETER
Differential Analog Input Bias Current
IBDIFF = (IB+ - IB-)
Full Power Input Bandwidth, FPBW
Analog Input Common Mode Voltage Range
(VIN+ + VIN-) / 2
REFERENCE INPUT
Total Reference Resistance, RL
Reference Current
Positive Reference Voltage Input, VREF+
Negative Reference Voltage Input, VREF-
Reference Common Mode Voltage
(VREF+ + VREF-) / 2
DC BIAS VOLTAGE
DC Bias Voltage Output, VDC
Maximum Output Current
DIGITAL INPUTS
Input Logic High Voltage, VIH
Input Logic Low Voltage, VIL
Input Logic High Current, IIH
Input Logic Low Current, IIL
Input Capacitance, CIN
DIGITAL OUTPUTS
Output Logic High Voltage, VOH
Output Logic Low Voltage, VOL
Output Three-State Leakage Current, IOZ
Output Logic High Voltage, VOH
Output Logic Low Voltage, VOL
Output Three-State Leakage Current, IOZ
Output Capacitance, COUT
TIMING CHARACTERISTICS
Aperture Delay, tAP
Aperture Jitter, tAJ
Data Output Hold, tH
Data Output Delay, tOD
Data Output Enable Time, tEN
Data Output Enable Time, tDIS
Data Latency, tLAT
Power-Up Initialization
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AVCC
Digital Supply Voltage, DVCC1
Digital Output Supply Voltage, DVCC2
Supply Current, ICC
Power Dissipation
TEST CONDITIONS
(Note 3)
Differential Mode (Note 2)
(Note 2)
(Note 2)
(Note 2)
CLK, DFS, OE
CLK, DFS, OE
CLK, DFS, OE, VIH = 5V
CLK, DFS, OE, VIL = 0V
IOH = 100µA; DVCC2 = 5V
IOL = 100µA; DVCC2 = 5V
VO = 0/5V; DVCC2 = 5V
IOH = 100µA; DVCC2 = 3V
IOL = 100µA; DVCC2 = 3V
VO = 0/5V; DVCC2 = 3V
For a Valid Sample (Note 2)
Data Invalid Time (Note 2)
At 3.0V
At 5.0V
VIN+ - VIN- = 1.25V and DFS = “0”
VI+ - VIN- = 1.25V and DFS = “0”
MIN TYP MAX UNITS
- ±0.5 -
µA
- 250 -
0.25 - 4.75
MHz
V
- 2.5K -
- 1.0 -
- 2.5 -
- 2.0 -
- 2.25 -
Ω
mA
V
V
V
- 3.2 -
V
- - 0.4 mA
2.0
-
-10.0
-10.0
-
--
- 0.8
- +10.0
- +10.0
7-
V
V
µA
µA
pF
4.0 -
-
- - 0.5
- ±1 ±10
2.4 -
-
- - 0.5
- ±1 ±10
- 10 -
V
V
µA
V
V
µA
pF
-5-
ns
- 5 - psRMS
-7-
ns
-8-
ns
-5-
ns
-5-
ns
- - 7 Cycles
- - 20 Cycles
4.75 5.0 5.25
4.75 5.0 5.25
2.7 3.0 3.3
4.75 5.0 5.25
- 52 -
- 260 -
V
V
V
V
mA
mW
35
5 Page 
HI5766
Detailed Description
Theory of Operation
The HI5766 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction logic. Figure 24 depicts
the circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
sampling clock which is a non-overlapping two phase signal, φ1
and φ2, derived from the master sampling clock. During the
sampling phase, φ1, the input signal is applied to the sampling
capacitors, CS. At the same time the holding capacitors, CH,
are discharged to analog ground. At the falling edge of φ1 the
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase, φ2, the two bottom plates of
the sampling capacitors are connected together and the
holding capacitors are switched to the op amp output nodes.
The charge then redistributes between CS and CH completing
one sample-and-hold cycle. The front end sample-and-hold
output is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-hold
function but will also convert a single-ended input to a fully-
differential output for the converter core. During the sampling
phase, the VIN pins see only the on-resistance of a switch and
CS. The relatively small values of these components result in a
typical full power input bandwidth of 250MHz for the converter.
VIN+
φ1
φ1
CS
φ2
VIN- φ1 CS
φ1
CH
-+
+-
CH
φ1
VOUT+
VOUT-
φ1
FIGURE 24. ANALOG INPUT SAMPLE-AND-HOLD
As illustrated in the functional block diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a
two-bit multiplying digital-to-analog converter, follow the S/H
circuit with the ninth stage being a two bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final
10-bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus on the 7th cycle of the clock after the analog
sample is taken. This time delay is specified as the data
latency. After the data latency time, the digital data
representing each succeeding analog sample is output during
the following clock cycle. The digital output data is
synchronized to the external sampling clock by a double
buffered latching technique. The output of the digital error
correction circuit is available in two’s complement or offset
binary format depending on the state of the Data Format
Select (DFS) control input (see Table 1, A/D Code Table).
Reference Voltage Inputs, VREF- and VREF+
The HI5766 is designed to accept two external reference
voltage sources at the VREF input pins. Typical operation of
the converter requires VREF+ to be set at +2.5V and VREF- to
be set at 2.0V. However, it should be noted that the input
structure of the VREF+ and VREF- input pins consists of a
resistive voltage divider with one resistor of the divider
(nominally 500Ω) connected between VREF+ and VREF- and
the other resistor of the divider (nominally 2000Ω) connected
between VREF- and analog ground. This allows the user the
option of supplying only the +2.5V VREF+ voltage reference
with the +2.0V VREF- being generated internally by the
voltage division action of the input structure.
The HI5766 is tested with VREF- equal to +2.0V and VREF+
equal to +2.5V yielding a fully differential analog input voltage
range of ±0.5V. VREF+ and VREF- can differ from the above
voltages.
In order to minimize overall converter noise it is
recommended that adequate high frequency decoupling be
provided at both of the reference voltage input pins, VREF+
and VREF-.
Analog Input, Differential Connection
The analog input to the HI5766 is a differential input that can
be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figure 25 and Figure 26) will give the
best performance for the converter.
VIN
-VIN
VIN+
R HI5766
VDC
R
VIN-
FIGURE 25. AC COUPLED DIFFERENTIAL INPUT
Since the HI5766 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V.
For the differential input connection this implies the analog
input common mode voltage can range from 0.25V to 4.75V.
41
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HI5766.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HI5760 | A/D Converter | Intersil Corporation |
| HI5762 | A/D Converter | Intersil Corporation |
| HI5766 | A/D Converter | Intersil Corporation |
| HI5767 | A/D Converter | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |