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PDF HI5741 Data sheet ( Hoja de datos )
| Número de pieza | HI5741 | |
| Descripción | A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HI5741 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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®
Data Sheet
September 20, 2006
HI5741
FN4071.12
14-Bit, 100MSPS, High Speed D/A
Converter
The HI5741 is a 14-bit, 100MSPS, D/A converter which is
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Operating from +5V and -5.2V, the converter provides
20.48mA of full scale output current and includes an input
data register and bandgap voltage reference. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented architecture. The digital inputs
are TTL/CMOS compatible and translated internally to ECL.
All internal logic is implemented in ECL to achieve high
switching speed with low noise. The addition of laser
trimming assures 14-bit linearity is maintained along the
entire transfer curve.
Ordering Information
PART
NUMBER
PART
TEMP.
PKG.
MARKING RANGE (°C) PACKAGE DWG. #
HI5741BIB HI5741BIB -40 to +85 28 Ld SOIC M28.3
HI5741BIB-T HI5741BIB 28 Ld SOIC Tape and Reel M28.3
HI5741BIBZ HI5741BIBZ -40 to +85 28 Ld SOIC M28.3
(Note)
www.DataSheet4U.com
(Pb-free)
HI5741BIBZ-T HI5741BIBZ 28 Ld SOIC Tape and Reel M28.3
(Note)
(Pb-free)
HI5741-EVS
+25 Evaluation Board
(SOIC)
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 100MSPS
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . . . 1 LSB
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . . . 1pV-s
• TTL/CMOS Compatible Inputs
• Improved Hold Time. . . . . . . . . . . . . . . . . . . . . . . . 0.25ns
• Excellent Spurious Free Dynamic Range
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Cellular Base Stations
• Wireless Communications
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• Test Equipment
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
Pinout
HI5741
(28 LD SOIC)
TOP VIEW
D13 (MSB) 1
D12 2
D11 3
D10 4
D9 5
D8 6
D7 7
D6 8
D5 9
D4 10
D3 11
D2 12
D1 13
D0 (LSB) 14
28 DGND
27 AGND
26 REF OUT
25 CTRL AMP OUT
24 CTRL AMP IN
23 RSET
22 AVEE
21 IOUT
20 IOUT
19 ARTN
18 DVEE
17 DGND
16 DVCC
15 CLOCK
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2001, 2003, 2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
Timing Diagrams
CLK
HI5741
50%
D13-D0
IOUT
ERROR BAND
V GLITCH AREA = 1/2 (H x W)
HEIGHT (H)
tPD tSETT
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
WIDTH (W)
t (ps)
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
CLK
D13-D0
IOUT
tPW1
tPW2
tSU tSU tSU
tHLD
tHLD
tHLD
tPD tSETT
50%
tSETT
tPD
tPD tSETT
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
5 FN4071.12
September 20, 2006
5 Page 
HI5741
to change before another. In order to minimize this, the
Intersil HI5741 employs an internal register, just prior to the
current sources, which is updated on the clock edge. Lastly,
the worst case glitch on traditional D/A converters usually
occurs at the major transition (i.e., code 8191 to 8192).
However, due to the split architecture of the HI5741, the
glitch is moved to the 1023 to 1024 transition (and every
subsequent 1024 code transitions thereafter). This split
R/2R segmented current source architecture, which
decreases the amount of current switching at any one time,
makes the glitch practically constant over the entire output
range. By making the glitch a constant size over the entire
output range this effectively integrates this error out of the
end application.
In measuring the output glitch of the HI5741 the output is
terminated into a 64Ω load. The glitch is measured at any
one of the current cell carry (code 1023 to 1024 transition or
any multiple thereof) throughout the DACs output range.
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 25 shows the area considered
as glitch when changing the DAC output. Units are typically
specified in picoVolt/seconds (pV/s).
HI5741
(21) IOUT
100MHz
LOW PASS
SCOPE
FILTER
64Ω
50Ω
FIGURE 24. GLITCH TEST CIRCUIT
a (mV)
GLITCH ENERGY = (a x t)/2
t (ns)
FIGURE 25. MEASURING GLITCH ENERGY
Applications
Bipolar Applications
To convert the output of the HI5741 to a bipolar 4V swing,
the following applications circuit is recommended. The
reference can only provide 125µA of drive, so it must be
buffered to create the bipolar offset current needed to
generate the -2V output with all bits ‘off’. The output current
must be converted to a voltage and then gained up and
offset to produce the proper swing. Care must be taken to
compensate for the voltage swing and error.
REF OUT
(26)
-
+
1/2 CA2904
5kΩ
5kΩ
-
+
1/2 CA2904
60Ω
HI5741
IOUT
(21)
0.1µF
50Ω
240Ω
240Ω
- VOUT
+
HFA1100
FIGURE 26. BIPOLAR OUTPUT CONFIGURATION
Interfacing to the HSP45106 NCO-16
The HSP45106 is a 16-bit Numerically Controlled Oscillator
(NCO). The HSP45106 can be used to generate various
modulation schemes for Direct Digital Synthesis (DDS)
applications. Figure 27 shows how to interface an HI5741 to
the HSP45106.
Definition of Specifications
Integral Linearity Error (INL) is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error (DNL) is the measure of the error
in step size between adjacent codes along the converter’s
transfer curve. Ideally, the step size is 1 LSB from one code to
the next, and the deviation from 1 LSB is known as DNL. A
DNL specification of greater than -1 LSB guarantees
monotonicity.
Feedthru is the measure of the undesirable switching noise
coupled to the output.
Output Voltage Full Scale Settling Time is the time
required from the 50% point on the clock input for a full scale
step to settle within an ±1/2 LSB error band.
Output Voltage Small Scale Settling Time is the time
required from the 50% point on the clock input for a 100mV
step to settle within an 1/2 LSB error band. This is used by
applications reconstructing highly correlated signals such as
sine waves with more than 5 points per cycle.
Glitch Area (GE) is the switching transient appearing on the
output during a code transition. It is measured as the area
under the curve and expressed as a volt • time specification
(typically pV-s).
Differential Gain (∆AV) is the gain error from an ideal sine
wave with a normalized amplitude.
Differential Phase (∆Φ) is the phase error from an ideal sine
wave.
11 FN4071.12
September 20, 2006
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HI5741.PDF ] | |
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