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PDF HI3026A Data sheet ( Hoja de datos )
| Número de pieza | HI3026A | |
| Descripción | Flash A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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March 2003
HI3026AINTP®EORSSSIOILBBPLSAEORSLTUENBTUSEMTPIBTRUEORTDEHUPIC3RT0O26D,UHCI3T824-6Bit, 140 MSPS, Flash A/D Converter
Features
• Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB
• Integral Linearity Error . . . . . . . . . . . . . . . . . . ±0.5 LSB
• Integral Linearity Compensation Circuit
• Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . 21pF
• Wide Analog Input Bandwidth . . . . . . . . . . . . . 150MHz
• Low Power Consumption . . . . . . . . . . . . . . . . . 790mW
• Internal 1/2 Frequency Divider Circuit (With Reset
Function)
• CLK/2 Clock Output Pin
• Compatible with ECL, PECL and TTL Digital Input Levels
• 1:2 Demultiplexed Output
• Direct Replacement for Sony CXA3026A
Applications
• RGB Graphics Processing (LCD, PDP)
• Digital Oscilloscopes
• Digital Communications (QPSK, QAM)
www.DataSheet4U.com
• Magnetic Recording (PRML)
Description
The HI3026A is an 8-bit, high-speed, flash analog-to-digital
converter optimized for high speed, low power, and ease of use.
With a 140 MSPS encode rate capability and full-power analog
bandwidth of 150MHz, this component is ideal for applications
requiring the highest possible dynamic performance.
To minimize system cost and power dissipation, only a +5V
power supply is required. The HI3026A’s clock input interfaces
directly to TTL, ECL, or PECL logic and will operate with single-
ended inputs. The user may select 16-bit demultiplexed output
or 8-bit single-channel digital outputs. The demultiplexed mode
interleaves the data through two 8-bit channels at 1/2 the clock
rate. Operation in demultiplexed mode reduces the speed and
cost of external digital interfaces, while allowing the A/D
converter to be clocked to the full 140 MSPS conversion rate.
Fabricated with an advanced bipolar process, the HI3026A is
provided in a space-saving 48-lead MQFP surface mount
plastic package and is specified over the -20oC to 75oC
temperature range.
Part Number Information
PART
NUMBER
HI3026AJCQ
HI3026AEVAL
TEMPT.
RANGE (oC)
-20 to 75
25
PACKAGE
PKG. NO.
48 Ld MQFP Q48.12x12-S
Evaluation Board
Pinout
HI3026A (MQFP)
TOP VIEW
DVEE3
VRB
AGND
VRM1
AVCC
VIN
VRM2
AVCC
VRM3
AGND
VRT
DGND3
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
P1D3
P1D2
P1D1
P1D0
DGND2
DVCC2
DVCC1
DGND1
P2D7
P2D6
P2D5
P2D4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
FN4246.1
1 page  
HI3026A
Electrical Specifications
TDAVC=C215,o2C,
AVCC, DGND3
(Continued)
=
+5V,
DGND1,
2,
AGND,
DVEE3
=
0V,
VRT
=
4V,
VRB
=
2V,
PARAMETER
SYMBOL
TEST CONDITIONS
Error Rate
fC = 140 MSPS, fIN = 1kHz
Full Scale, DMUX Mode,
Error > 16 LSB
fC = 140 MSPS,
fIN = 34.999MHz Full Scale,
DMUX Mode, Error > 16 LSB
fC = 100 MSPS,
fIN = 24.999MHz Full Scale,
Straight Mode, Error > 16 LSB
POWER SUPPLY
Supply Current
ICC
Supply Current
IEE
Power Consumption (Note 8)
PD
NOTES:
4. RREF: Resistance value between VRT and VRB.
5.
IREF
=
V-----R----T-----–----V----R-----B-
RREF
.
6. t = --1--- .
fC
7. TPS = Times Per Sample.
8.
PD
=
(
IC
C
+
IE
E
)
•
VC
C
+
(---V----R----T-----–-----V----R----B----)--2--
VREF
.
MIN
-
-
-
130
0.4
690
TYP
-
-
-
MAX
10-12
10-9
10-9
150 190
0.6 0.8
790 990
Timing Waveforms
UNITS
TPS
TPS
TPS
(Note 7)
mA
mA
mW
VIN
CLK
P1D0 TO D7
P2D0 TO D7
CLK OUT
N-1
tDS
4.5ns
t
N+2
N+3
N N+1
tPW1 tPW0
tDCLK
7ns
2.0V
0.8V
tDO2
8ns
N-2
N-3
tDO1
T + 1ns
2.0V
0.8V
2.0V
0.8V
N
2.0V
0.8V
N-1
N+2
N+1
RESET PULSE
tPWR
FIGURE 1. DEMUX MODE TIMING CHART (SELECT = VCC)
5
5 Page 
HI3026A
clock applied to the A/D converter as the system clock.
The A/D converter can operate at fC (Min) = 100 MSPS in
this mode.
Digital Input Level and Supply Voltage Settings
The logic input level for the HI3026A supports ECL, PECL
and TTL levels.
The power supplies (DVEE3, DGND3) for the logic input
block must be set to match the logic input (CLK and RESET
signals) level.
TABLE 3. LOGIC INPUT LEVEL AND POWER SUPPLY
SETTINGS
DIGITAL
INPUT
LEVEL
ECL
PECL
TTL
DVEE3
-5V
0V
0V
DGND3
0V
+5V
+5V
SUPPLY
VOLTAGE
±5V
+5V
+5V
APPLICATION
CIRCUITS
(FIGURE)
(18) (21)
(19) (22)
(20) (23)
CLK
HI3026A
CLK A
RESETN
HI3026A
CLK B
RESETN
CLK
8 BITS
CLKOUT
DATA
8 BITS
CLKOUT
DATA
FIGURE 9. WHEN THE RESET PULSE IS NOT USED
CLK
RESET PULSE
HI3026A
CLK A
RESETN
8 BITS
CLK
RESET
PULSE
CLKOUT
DATA
HI3026A
CLK B
RESETN
8 BITS
CLKOUT
DATA
FIGURE 10. WHEN THE RESET PULSE IS USED
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet HI3026A.PDF ] | |
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