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HI20203 の電気的特性と機能

HI20203のメーカーはIntersil Corporationです、この部品の機能は「Ultra High-Speed D/A Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 HI20203
部品説明 Ultra High-Speed D/A Converter
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HI20203 Datasheet, HI20203 PDF,ピン配置, 機能
August 2000
HI20203F® Oc1oR-8n8Ata8Pc-ItONOoTSBuESSrRIOBTSLeLIcELEhToSnErUicPwBaRwlSOSTwuDI.TipUnUptCTeoTErrst PiCl.RceoOnmtDe/UrtsaCctT
Ultra
8-Bit, 160 MSPS,
High-Speed D/A Converter
Features
Description
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 160MHz
• 8-Bit (HI20203) Resolution
• Differential Linearity Error . . . . . . . . . . . . . . . . 0.5 LSB
• Low Glitch Noise
• Analog Multiplying Function
• Low Power Consumption . . . . . . . . . . . . . . . . . . 420mW
• Evaluation Board Available
• Direct Replacement for the Sony CX20201-3, CX20202-3
Applications
• Wireless Communications
• Signal Reconstruction
The HI20203 is an 8-bit, 160MHz ultra high speed D/A con-
verter. The converter is based on an R2R switched current
source architecture that includes an input data register with
a complement feature and is Emitter Coupled Logic (ECL)
compatible.
The HI20203 is an 8-bit accurate D/A with a linearity error of
0.5 LSB.
For 10-bit resolution, please refer to the HI20201 data sheet.
Part Number Information
PART
NUMBER
HI20203JCB
TEMP.
RANGE (oC)
PACKAGE
-20 to 75 28 Ld SOIC
PKG. NO.
M28.3A-S
• Direct Digital Synthesis
• High Definition Video Systems
• Digital Measurement Systems
www.DataSheet4U.com
• Radar
Pinout
HI20203
(PDIP, SOIC)
TOP VIEW
(MSB) D7 1
D6 2
D5 3
D4 4
D3 5
D2 6
D1 7
D0 8
NC 9
NC 10
NC 11
NC 12
CLK 13
CLK 14
28 AVSS
27 VREF
26 AVEE
25 NC
24 NC
23 NC
22 NC
21 NC
20 IOUT
19 NC
18 AVSS
17 DVSS
16 COMPL
15 DVEE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
File Number 4096.2

1 Page





HI20203 pdf, ピン配列
HI20203
Absolute Maximum Ratings TA = 25oC
Digital Supply Voltage DVEE to DVSS . . . . . . . . . . . . . . . . . . . -7.0V
Analog Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . . -7.0V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 to DVEE V
Reference Input Voltage. . . . . . . . . . . . . . . . . . . . . . +0.3 to AVEE V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Operating Conditions
Thermal Information
Thermal Resistance (Typical, Note 5)
θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Supply Voltage
AVEE, DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.75V to -5.45V
AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to +0.05V
Digital Input Voltage
VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to -0.7V
VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.9V to -1.6V
Reference Input Voltage, VREE . . . . . . . VEE + 0.5V to VEE + 1.4V
Load Resistance, RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . Above 75
Output Voltage, VO(FS)
Temperature Range . .
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. 0.8V to 1.2V
-20oC to 75oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AVEE = -5.2V, DVEE = -5.2V, AGND = 0V, DGND = 0V, RL = , VOUT = -1V, TA = 25oC
HI20203JCB/JCP
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE
Resolution
8 - - Bits
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, VOS
(Adjustable to Zero)
fS = 160MHz (End Point)
fS = 160MHz
(Note 3)
- - ±0.5 LSB
-
-
±0.50
LSB
- 1.8 - LSB
Full Scale Error, FSE
(Adjustable to Zero)
(Note 3)
- - ±26 LSB
Full Scale Output Current, IFS
DYNAMIC CHARACTERISTICS
- - 20 mA
Throughput Rate
See Figure 11
160 -
- MHz
Glitch Energy, GE
REFERENCE INPUT
ROUT = 75
- 15 - pV/s
Voltage Reference Input Range
Reference Input Current
Voltage Reference to Output Small
Signal Bandwidth
With respect to AVEE
VREF = -4.58V
-3dB point 1VP-P Input
+0.5
-0.1
-
-
-0.4
14.0
+1.4
-3.0
-
V
µA
MHz
Output Rise Time, tr
Output Fall Time, tf
DIGITAL INPUTS
RLOAD = 75
RLOAD = 75
- 1.5 - ns
- 1.5 - ns
Input Logic High Voltage, VIH
Input Logic Low Voltage, VIL
(Note 2)
(Note 2)
-1.0 -0.89
-1.75
-1.6
V
V
3


3Pages


HI20203 電子部品, 半導体
HI20203
Pin Descriptions
28 PIN SOIC
28
PIN NAME
AVSS
Analog Ground
PIN DESCRIPTION
Detailed Description
The HI20203 is an 8-bit, current-output D/A converter. The
converter has 10 data bits but yields 8-bit performance.
Architecture
The HI20203 is a combined R2R/segmented current source
design. The 6 least significant bits of the converter are derived by
a traditional R2R network to binary weight the 1mA current
sources. The upper 4 most significant bits are implemented as
segmented or thermometer encoded current sources. The
encoder converts the incoming 4 bits to 15 control lines to enable
the most significant current sources. The thermometer encoder
will convert binary to individual control lines. See Table 1.
MSB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TABLE 1. THERMOMETER ENCODER
BIT 6
0
BIT 5
0
BIT 4
0
THERMOMETER CODE
1 = ON, 0 = OFF
I15 - I0
000 0000 0000 0000
0 0 1 000 0000 0000 0001
0 1 0 000 0000 0000 0011
0 1 1 000 0000 0000 0111
1 0 0 000 0000 0000 1111
1 0 1 000 0000 0001 1111
1 1 0 000 0000 0011 1111
1 1 1 000 0000 0111 1111
0 0 0 000 0000 1111 1111
0 0 1 000 0001 1111 1111
0 1 0 000 0011 1111 1111
0 1 1 000 0111 1111 1111
1 0 0 000 1111 1111 1111
1 0 1 001 1111 1111 1111
1 1 0 011 1111 1111 1111
1 1 1 111 1111 1111 1111
01 1111 1111 to 10 0000 0000. But in the HI20203 the glitch
is moved to the 00 0001 1111 to 11 1110 0000 transition. This
is achieved by the split R2R/segmented current source
architecture. This decreases the amount of current switching
at any one time and makes the glitch practically constant over
the entire output range. By making the glitch a constant size
over the entire output range this effectively integrates this
error out of the end application.
In measuring the output glitch of the HI20203 the output is
terminated into a 75load. The glitch is measured at the
major carry’s throughout the DACs output range.
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 7 shows the area considered
as glitch when changing the DAC output. Units are typically
specified in picoVolt/seconds (pV/s).
HI20203
(20) IOUT
34MHz
LOW PASS
SCOPE
FILTER
7550
FIGURE 6. HI20203 GLITCH TEST CIRCUIT
A (mV)
GLITCH ENERGY = (a x t)/2
The architecture of the HI20203 is designed to minimize glitch
while providing a manufacturable 10-bit design that does not
require laser trimming to achieve good linearity.
Glitch
Glitch is caused by the time skew between bits of the
incoming digital data. Typically the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time (TTL designs). In an ECL system
where the logic levels switch from one non-saturated level to
another, the switching times can be considered close to
symmetrical. This helps to reduce glitch in the D/A. Unequal
delay paths through the device can also cause one current
source to change before another. To minimize this the Intersil
HI20203 employs an internal register, just prior to the current
sources, that is updated on the clock edge. Lastly the worst
case glitch usually happens at the major transition i.e.,
t (ns)
FIGURE 7. GLITCH ENERGY
Setting Full Scale
The Full Scale output voltage is set by the Voltage Refer-
ence pin (27). The output voltage performance will vary as
shown in Figure 2.
The output structure of the HI20203 can handle down to a
75load effectively. To drive a 50load Figure 8 is
6

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共有リンク

Link :


部品番号部品説明メーカ
HI20201

10-Bit Ultra High Speed D/A Converter

Intersil
Intersil
HI20203

Ultra High-Speed D/A Converter

Intersil Corporation
Intersil Corporation
HI20206

3-Channel D/A Converter

Intersil Corporation
Intersil Corporation


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