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HI7191 の電気的特性と機能

HI7191のメーカーはIntersil Corporationです、この部品の機能は「Sigma Delta A/D Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 HI7191
部品説明 Sigma Delta A/D Converter
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HI7191 Datasheet, HI7191 PDF,ピン配置, 機能
HI7191
March 1998
24-Bit, High Precision,
Sigma Delta A/D Converter
Features
• 22-Bit Resolution with No Missing Code
• 0.0007% Integral Non-Linearity (Typ)
• 20mV to ±2.5V Full Scale Input Ranges
• Internal PGIA with Gains of 1 to 128
• Serial Data I/O Interface, SPI Compatible
• Differential Analog and Reference Inputs
• Internal or System Calibration
• -120dB Rejection of 60/50Hz Line Noise
• Settling Time of 4 Conversions (Max) for a Step Input
Applications
• Process Control and Measurement
• Industrial Weight Scales
• Part Counting Scales
• Laboratory Instrumentation
• Seismic Monitoring
• Magnetic Field Monitoring
• Additional Reference Literature
- TB348 “HI7190/1 Negative Full Scale Error vs
Conversion Frequency”
- AN9504 “A Brief Intro to Sigma Delta Conversion”
- TB329 “Intersil Sigma Delta Calibration Technique”
- AN9505 “Using the HI7190 Evaluation Kit”
- TB331 “Using the HI7190 Serial Interface”
- AN9527 “Interfacing HI7190 to a Microcontroller”
- AN9532 “Using HI7190 in a Multiplexed System”
- AN9601 “Using HI7190 with a Single +5V Supply”
Description
The Intersil HI7191 is a monolithic instrumentation, sigma delta
A/D converter which operates from ±5V supplies. Both the sig-
nal and reference inputs are fully differential for maximum flexi-
bility and performance. An internal Programmable Gain
Instrumentation Amplifier (PGIA) provides input gains from 1 to
128 eliminating the need for external pre-amplifiers. The on-
demand converter auto-calibrate function is capable of remov-
ing offset and gain errors existing in external and internal cir-
cuitry. The on-board user programmable digital filter provides
over -120dB of 60/50Hz noise rejection and allows fine tuning
of resolution and conversion speed over a wide dynamic range.
The HI7191 and HI7191 are functionally the same device so all
discussion will refer to the HI7191 for simplicity.
The HI7191 contains a serial I/O port and is compatible with
most synchronous transfer formats including both the Motor-
ola 6805/11 series SPI and Intel 8051 series SSR protocols.
A sophisticated set of commands gives the user control over
calibration, PGIA gain, device selection, standby mode, and
several other features. The On-chip Calibration Registers
allow the user to read and write calibration data.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HI7191IP
-40 to 85 20 Ld PDIP
HI7191IB
-40 to 85 20 Ld SOIC
HI7190EVAL
Evaluation Kit
PKG.
NO.
E20.3
M20.3
Pinout
HI7191
(PDIP, SOIC)
TOP VIEW
SCLK 1
SDO 2
SDIO 3
CS 4
DRDY 5
DGND 6
AVSS 7
VRLO 8
VRHI 9
VCM 10
20 MODE
19 SYNC
18 RESET
17 OSC1
16 OSC2
15 DVDD
14 AGND
13 AVDD
12 VINHI
11 VINLO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1897
File Number 4138.3

1 Page





HI7191 pdf, ピン配列
HI7191
Absolute Maximum Ratings
Supply Voltage
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVSS to AVDD
Digital Input, Output and I/O Pins . . . . . . . . . . . . . . . DGND to DVDD
ESD Tolerance (No Damage)
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +100V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications AVDD = +5V, AVSS = -5V, DVDD = +5V, VRHI = +2.5V, VRLO = AGND = 0V, VCM = AGND,
PGIA Gain = 1, OSCIN = 10MHz, Bipolar Input Range Selected, fN = 10Hz
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
SYSTEM PERFORMANCE
Integral Non-Linearity, INL
End Point Line Method (Notes 3, 5, 6)
-
±0.0007 ±0.0015
%FS
Differential Non-Linearity
(Note 2)
No Missing codes to 22-Bits
LSB
Offset Error, VOS
Offset Error Drift
See Table 1
VINHI = VINLO (Notes 3, 8)
---
-
- 1 - µV/ oC
Full Scale Error, FSE
VINHI - VINLO = +2.5V (Notes 3, 5, 8, 10)
-
-
-
-
Noise, eN
See Table 1
---
-
Common Mode Rejection Ratio, CMRR VCM = 0V, VINHI = VINLO from -2V to +2V
-70 -
dB
Normal Mode 50Hz Rejection
Filter Notch = 10Hz, 25Hz, 50Hz (Note 2)
-120
-
-
dB
Normal Mode 60Hz Rejection
Filter Notch = 10Hz, 30Hz, 60Hz (Note 2)
-120
-
-
dB
Step Response Settling Time
- 2 4 Conversions
ANALOG INPUTS
Input Voltage Range
Input Voltage Range
Common Mode Input Range
Input Leakage Current, IIN
Input Capacitance, CIN
Reference Voltage Range, VREF
(VREF = VRHI - VRLO)
Transducer Burn-Out Current, IBO
CALIBRATION LIMITS
Unipolar Mode (Note 9)
Bipolar Mode (Note 9)
(Note 2)
VIN = AVDD (Note 2)
0
- VREF
AVSS
-
-
2.5
-
-
-
-
-
5.0
-
200
VREF
VREF
AVDD
1.0
-
5
-
V
V
V
nA
pF
V
nA
Positive Full Scale Calibration Limit
Negative Full Scale Calibration Limit
Offset Calibration Limit
Input Span
DIGITAL INPUTS
- - 1.2(VREF/Gain)
- - 1.2(VREF/Gain)
- - 1.2(VREF/Gain)
0.2(VREF/Gain) - 2.4(VREF/Gain)
-
-
-
-
Input Logic High Voltage, VIH
Input Logic Low Voltage, VIL
Input Logic Current, II
(Note 11)
VIN = 0V, +5V
2.0 -
-
- - 0.8
- 1.0 10
V
V
µA
1899


3Pages


HI7191 電子部品, 半導体
HI7191
Pin Descriptions
20 LEAD
DIP, SOIC PIN NAME
DESCRIPTION
1 SCLK Serial Interface Clock. Synchronizes serial data transfers. Data is input on the rising edge and output on the
falling edge.
2 SDO Serial Data OUT. Serial data is read from this line when using a 3-wire serial protocol such as the
Motorola Serial Peripheral Interface.
3 SDIO Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial
Interface using a 2-wire serial protocol.
4 CS Chip Select Input. Used to select the HI7191 for a serial data transfer cycle. This line can be tied to DGND.
5 DRDY An Active Low Interrupt indicating that a new data word is available for reading.
6 DGND Digital Supply Ground.
7 AVSS Negative Analog Power Supply (-5V).
8 VRLO External Reference Input. Should be negative referenced to VRHI.
9 VRHI External Reference Input. Should be positive referenced to VRLO.
10 VCM Common Mode Input. Should be set to halfway between AVDD and AVSS.
11 VINLO Analog Input LO. Negative input of the PGIA.
12 VINHI Analog Input HI. Positive input of the PGIA. The VINHI input is connected to a current source that can be used to check
the condition of an external transducer. This current source is controlled via the Control Register.
13 AVDD Positive Analog Power Supply (+5V).
14 AGND Analog Supply Ground.
15 DVDD Positive Digital Supply (+5V).
16 OSC2 Used to connect a crystal source between OSC1 and OSC2. Leave open otherwise.
17 OSC1 Oscillator Clock Input for the device. A crystal connected between OSC1 and OSC2 will provide a clock to the
device, or an external oscillator can drive OSC1. The oscillator frequency should be 10MHz (Typ).
18 RESET Active Low Reset Pin. Used to initialize the HI7191 registers, filter and state machines.
19 SYNC Active Low Sync Input. Used to control the synchronization of a number of HI7191s. A logic ‘0’ initializes the converter.
20 MODE Mode Pin. Used to select between Synchronous Self Clocking (Mode = 1) or Synchronous External Clocking
(Mode = 0) for the Serial Port.
Load Test Circuit
V1
ESD Test Circuits
R1 R2
V±
CESD DUT
FIGURE 5A.
DUT
R1
CL (INCLUDES STRAY
CAPACITANCE)
FIGURE 4.
HUMAN BODY
CESD = 100pF
R1 = 10M
R2 = 1.5k
MACHINE MODEL
CESD = 200pF
R1 = 10M
R2 = 0
R1
V ± R2
DUT
CHARGED DEVICE MODEL
R1 = 1G
R2 = 1
DIELECTRIC
FIGURE 5B.
1902

6 Page



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部品番号部品説明メーカ
HI7190

Sigma Delta A/D Converter

Intersil Corporation
Intersil Corporation
HI7191

Sigma Delta A/D Converter

Intersil Corporation
Intersil Corporation


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