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UPD780143A の電気的特性と機能

UPD780143AのメーカーはNECです、この部品の機能は「(UPD78014x) 8-bit single-chip microcontroller」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD780143A
部品説明 (UPD78014x) 8-bit single-chip microcontroller
メーカ NEC
ロゴ NEC ロゴ 




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UPD780143A Datasheet, UPD780143A PDF,ピン配置, 機能
User’s Manual
78K0/KF1
8-Bit Single-Chip Microcontrollers
µPD780143www.DataSheet4U.com µPD780143(A) µPD780143(A1) µPD780143(A2)
µPD780144 µPD780144(A) µPD780144(A1) µPD780144(A2)
µPD780146 µPD780146(A) µPD780146(A1) µPD780146(A2)
µPD780148 µPD780148(A) µPD780148(A1) µPD780148(A2)
µPD78F0148 µPD78F0148(A) µPD78F0148(A1)
Document No. U15947EJ2V0UD00 (2nd edition)
Date Published September 2003 N CP(K)
©
Printed in Japan

1 Page





UPD780143A pdf, ピン配列
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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
User’s Manual U15947EJ2V0UD
3


3Pages


UPD780143A 電子部品, 半導体
Major Revisions in This Edition (1/3)
Page
Description
Throughout
Addition of products
µPD78F0148(A1), 780143(A2), 780144(A2), 780146(A2), 780148(A2)
Under development Under mass production
µPD780143, 780144, 780146, 780148, 78F0148, 780143(A), 780144(A), 780146(A), 780148(A), 78F0148(A),
780143(A1), 780144(A1), 780146(A1), 780148(A1)
Modification of names of the following special function registers (SFRs)
Ports 0 to 7, and 12 to 14 Port registers 0 to 7, and 12 to 14
p.38 Addition of Cautions 3 and 4 to 1.4 Pin Configuration (Top View)
p.40
Modification of 1.5 K1 Family Lineup
p.45 Modification of outline of timer in and addition of Remark to 1.7 Outline of Functions
p.47 Addition of Table 2-1 Pin I/O Buffer Power Supplies
pp.55, 56
Modification of descriptions in 2.2.12 AVREF, 2.2.15 REGC, and 2.2.20 VPP (flash memory versions only)
pp.57, 58
Modification of the following contents in Table 2-2 Pin I/O Circuit Types
Modification of recommended connection when P60 to P63 are not used
Modification of I/O circuit type of P62 and P63
Addition of Note to AVREF
Modification of recommended connection when VPP is not used
pp.62 to 66
Modification of Figure 3-1 Memory Map (µPD780143) to Figure 3-5 Memory Map (µPD78F0148)
p.76 Modification of Figure 3-14 Data to Be Saved to Stack Memory
p.77 Modification of Figure 3-15 Data to Be Restored from Stack Memory
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p.90
pp.93 to 95
Modification of [Description example] in 3.4.4 Short direct addressing
Addition of [Illustration] to 3.4.7 Based addressing, 3.4.8 Based indexed addressing, and 3.4.9 Stack
addressing
p.96 Addition of Table 4-1 Pin I/O Buffer Power Supplies
p.98 Modification of Table 4-3 Port Configuration
pp.108, 111, 112, Modification of Figure 4-11 Block Diagram of P20 to P27, Figure 4-14 Block Diagram of P40 to P47,
114, 115
Figure 4-15 Block Diagram of P50 to P57, Figure 4-17 Block Diagram of P64, P65, and P67, and Figure
4-18 Block Diagram of P66
p.118
Addition of Remark to Figure 4-21 Block Diagram of P130
p.123
Deletion of input switch control register (ISC) from and addition of port registers (P0 to P7, P12 to P14) to 4.3
Registers Controlling Port Function
p.124
Modification of setting of output latch of P40 to P47, P50 to P57, P64, P65, and P67 in and addition of Note 2
to Table 4-5 Settings of Port Mode Register and Output Latch When Using Alternate Function
p.128
Partial modification of descriptions in 4.4.1 (1) Output mode, 4.4.3 (1) Output mode, and (2) Input mode
p.129
Addition of Caution to 5.1 External Bus Interface
p.132
Addition of Note to Figure 5-2 Format of Memory Expansion Mode Register (MEM)
p.134
Addition of Caution 2 to Figure 5-4 Format of Memory Expansion Wait Setting Register (MM)
p.139
Addition of Remark to Figure 5-8 External Memory Read Modify Write Timing
p.142
Modification of Figure 6-1 Block Diagram of Clock Generator
p.143
Addition of Note to 6.3 (1) Processor clock control register (PCC)
6 User’s Manual U15947EJ2V0UD

6 Page



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部品番号部品説明メーカ
UPD780143

(UPD78014x) 8-bit single-chip microcontroller

NEC
NEC
UPD780143A

(UPD78014x) 8-bit single-chip microcontroller

NEC
NEC


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