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USB97C102 の電気的特性と機能

USB97C102のメーカーはSMSC Corporationです、この部品の機能は「Multi-Endpoint USB Peripheral Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 USB97C102
部品説明 Multi-Endpoint USB Peripheral Controller
メーカ SMSC Corporation
ロゴ SMSC Corporation ロゴ 




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USB97C102 Datasheet, USB97C102 PDF,ピン配置, 機能
USB97C102
Multi-Endpoint USB Peripheral Controller with
Integrated 5 Port HUB
www.DataSheet4U.com
FEATURES
!" High Performance USB Peripheral Controller
Engine
- Integrated USB Transceiver
- Serial Interface Engine (SIE)
- 8051 Microcontroller (MCU)
- Patented Memory Management Unit (MMU)
- 4 Channel 8237 DMA Controller (ISADMA)
- 4K Byte On Board USB Packet Buffer
- Quasi-ISA Peripheral Interface
- USB Bus Snooping Capabilities
- GPIOs
!" Pin Compatible with SMSC USB97C100
!" Complete USB Specification 1.1 Compatibility
- Isochronous, Bulk, Interrupt, and Control Data
Independently Configurable per Endpoint
- Dynamic Hardware Allocation of -Packet
Buffer for Virtual Endpoints
- Multiple Virtual Endpoints (up to 16 TX, 16 RX
Simultaneously)
- Multiple Alternate Address Filters
- Dynamic Endpoint Buffer Length Allocation (0-
1280 Byte Packets)
!" USB Full (12Mbps) and Low Speed Capability
!" MMU and SRAM Buffer Allow Buffer Optimization
and Maximum Utilization of USB Bandwidth
- 128 Byte Page Size
- 10 Pages Maximum per Packet
- 32 Deep Receive Packet Queue
- Up to 5 Deep Transmit Packet Queue, per
Endpoint
- Hardware Generated Packet Header Records
Each Packet Status Automatically
- Simultaneous Arbitration Between MCU, SIE,
and ISA DMA Accesses
!" Extended Power Management
- Standard 8051 "Stop Clock" Modes
- Additional USB and ISA Suspend Resume
Events
- Internal 8MHz Ring Oscillator for Immediate
Low Power Code Execution
- 24, 16, 12, 8, 4, and 2 MHz PLL Taps For on
the Fly MCU and DMA Clock Switching
- Independent Clock/Power Management for
SIE, MMU, DMA and MCU
!" DMA Capability with ISA Memory
- Four Independent Channels
- Transfer Between Internal and External
Memory
- Transfer Between I/O and Internal Memory
- External Bus Master Capable
!" Scatter Gather DMA
- Four Independent Channels
- Up to 16 Transfers can be Programmed to
Occur Consecutively Without MCU
InterventionExternal MCU Memory Interface
- 1M Byte Code and Data Storage via 16K
Windows
- Flash, SRAM, or EPROM
- Downloadable via USB, Serial Port, or ISA
Peripheral
!" Quasi-ISA Interface Allows Interface to New and
"Legacy" Peripheral Devices
- 1M ISA Memory Space via 4K MCU Window
- 64K ISA I/O Space via 256 Byte MCU Window
- 4 External Interrupt Inputs
- 4 DMA Channels
- Variable Cycle Timing
- 8 Bit Data Path
!" 3.3 Volt, Low Power Operation
!" 5 Volt Tolerant Operation on I/O Signal Pins
!" On Board Crystal Driver Circuit
!" 128 Pin QFP Package
GENERAL DESCRIPTION
The USB97C102 is a flexible, general purpose USB peripheral interface and controller ideally suited for multiple
endpoint applications. The USB97C102 provides an ISA-like bus interface, which will allow virtually any PC peripheral
to be placed at the end of a USB connection. Its unique dynamic buffer architecture overcomes the throughput
disadvantages of existing fixed FIFO buffer schemes allowing maximum utilization of the USB connection’s overall
bandwidth. This architecture minimizes the integrated microcontroller’s participation in the USB data flow, allowing
back-to-back packet transfers to block oriented devices. The efficiency of this architecture allows floppy drives to
coexist with other peripherals such as serial and parallel ports on a single USB link.
SMSC DS – USB97C102
Rev. 03/23/2000

1 Page





USB97C102 pdf, ピン配列
TABLE OF CONTENTS
FEATURES ....................................................................................................................................................................... 1
GENERAL DESCRIPTION ............................................................................................................................................... 1
PIN CONFIGURATION ..................................................................................................................................................... 4
DESCRIPTION OF PIN FUNCTIONS............................................................................................................................... 5
BUFFER TYPE DESCRIPTIONS...................................................................................................................................... 7
CODE DEBUGGER INTERFACE................................................................................................................................ 7
FUNCTIONAL DESCRIPTION.......................................................................................................................................... 9
Serial Interface Engine (SIE) ......................................................................................................................................... 9
Micro Controller Unit (MCU) .......................................................................................................................................... 9
SIEDMA 9
Memory Management Unit (MMU) Register Description ............................................................................................... 9
ISADMA 9
Applications ................................................................................................................................................................... 9
Code Space................................................................................................................................................................. 12
Data Space.................................................................................................................................................................. 13
ISADMA Memory Map................................................................................................................................................. 15
MCU Block Register Summary .................................................................................................................................... 15
SGDMA Block Register Summary ............................................................................................................................... 16
MMU Block Register Summary ................................................................................................................................... 17
SIE Block Register Summary ...................................................................................................................................... 17
MCU REGISTER DESCRIPTION ................................................................................................................................... 19
MCU Runtime Registers.............................................................................................................................................. 19
FIFO Status Registers ................................................................................................................................................. 22
MCU ISA Interface Registers ...................................................................................................................................... 29
8237 (ISADMA) REGISTER DESCRIPTION .................................................................................................................. 31
Memory Map ............................................................................................................................................................... 31
Runtime Registers ....................................................................................................................................................... 33
MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION ........................................................................... 44
MMU Interface Registers............................................................................................................................................. 44
MMU Free Pages Register.............................................................................................................................................. 47
32 BYTE DEEP TX COMPLETION FIFO REGISTER .................................................................................................... 47
Tx FIFO POP Register .................................................................................................................................................... 49
SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION ................................................................................. 52
Packet Header Definition............................................................................................................................................. 52
SIE Interface Registers................................................................................................................................................ 53
ALTERNATE ADDRESS ENDPOINT MAPPING............................................................................................................ 56
Multiple Endpoint Mapping .......................................................................................................................................... 56
USB HUB BLOCK ........................................................................................................................................................... 64
SIU System Interface Unit ........................................................................................................................................... 64
HIU Hub Interface Unit ................................................................................................................................................ 64
HUB Block Register Summary..................................................................................................................................... 65
Disconnecting the USB Hub from the USB function .................................................................................................... 67
USB97C100 Compatibility Mode ................................................................................................................................. 67
DC PARAMETERS ......................................................................................................................................................... 68
MAXIMUM GUARANTEED RATINGS ........................................................................................................................ 68
USB PARAMETERS ....................................................................................................................................................... 70
USB DC PARAMETERS ............................................................................................................................................. 70
USB AC PARAMETERS ............................................................................................................................................. 71
MECHANICAL OUTLINE ................................................................................................................................................ 80
SMSC DS – USB97C102
Page 3
Rev. 03/23/2000


3Pages


USB97C102 電子部品, 半導体
QFP PIN
NUMBER
30
31
99
33
87, 86
96, 94, 92,
90.
95, 93, 91,
89.
85, 84, 83,
82, 81, 78,
79, 77.
45-52
75, 74, 68,
65, 64, 69,
70, 63, 73,
43, 72, 71,
62-58,
56-54
42
66
44
98
25,57,76,
101,121
8, 20, 32, 53,
67, 80, 88,
97, 116
41-34
27
SYMBOL
XTAL1/
Clock In
XTAL2
EXTCLK
CLKOUT
USBD-
USBD+
nPWREN[5:2]
nPWROK[5:2]
nPD+[5:2],
nPD -[5:2]
FD[7:0]
FA[19:0]
PIN DESCRIPTION
24MHz Crystal or clock input.
This pin can be connected to one terminal of the crystal or can be
connected to an external clock when a crystal is not used.
24MHz Crystal
This is the other terminal of the crystal.
Alternate clock to 8237
An external clock can be used for the internal 8237. This clock can be
used to synchronize the 8237 to other devices.
Clock output.
This clock frequency is the same as the 8051 running clock.
This clock is stopped when the 8051 is stopped. Peripherals should not
use this clock when they are expected to run when the 8051 is stopped.
This clock can be used to synchronize other devices to the 8051.
USB INTERFACE
USB Upstream Connection signals
These are two point-to-point signals and driven differentially.
USB Power Enable
A low signal on this pin applies power to the associated USB port (port
#5 through #2). This output signal is active low.
USB Over-Current Sense
Input to indicate an over-current condition for a bus powered USB
device on an external downstream port (port #5 through #2).
USB Downstream Connection Signals
These are two point-to-point signals and driven differentially. They are
used as standard “Walk Up” USB Port Connections
FLASH INTERFACE
Flash ROM Data Bus
These signals are used to transfer data between 8051 and the external
FLASH.
Flash ROM Address Bus
These signals address memory locations within the FLASH.
NFRD
NFWR
nFCE
FALE
VCC
GND
Flash ROM Read; active low
Flash ROM Write; active low
Flash ROM Chip Select; active low
Flash ROM address latch enable
POWER SIGNALS
+3.3 Volt Power
Ground Reference
GPIO[7:0]
PWRGD
MISCELLANEOUS
General Purpose I/O.
These pins can be configured as inputs or outputs under software
control.
Active high input.
This signal is used to indicate to that chip that a good power level has
been reached. When inactive/low, all pins are Tri-stated except
TST_OUT and a POR is generated.
BUFFER
TYPE
ICLKx
OCLKx
ICLK
O8
IOUSB
O24
I
IOUSB
IO8
O8
O8
O8
O8
O8
I/O24
I
SMSC DS – USB97C102
Page 6
Rev. 03/23/2000

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
USB97C100

Multi-Endpoint USB Peripheral Controller

SMSC Corporation
SMSC Corporation
USB97C102

Multi-Endpoint USB Peripheral Controller

SMSC Corporation
SMSC Corporation


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