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USB97C100 の電気的特性と機能

USB97C100のメーカーはSMSC Corporationです、この部品の機能は「Multi-Endpoint USB Peripheral Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 USB97C100
部品説明 Multi-Endpoint USB Peripheral Controller
メーカ SMSC Corporation
ロゴ SMSC Corporation ロゴ 




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USB97C100 Datasheet, USB97C100 PDF,ピン配置, 機能
USB97C100
ADVANCE INFORMATION
www.DataSheet4U.com
Multi-Endpoint USB Peripheral Controller
FEATURES
High Performance USB Peripheral Controller
Engine
- Integrated USB Transceiver
- Serial Interface Engine (SIE)
- 8051 Microcontroller (MCU)
- Patented Memory Management Unit (MMU)
- 4 Channel 8237 DMA Controller
(ISADMA)
- 4K Byte On Board USB Packet Buffer
- Quasi-ISA Peripheral Interface
- USB Bus Snooping Capabilities
- GPIOs
Complete USB Specification 1.1 Compatibility
- Isochronous, Bulk, Interrupt, and Control
Data Independently Configurable per
Endpoint
- Dynamic Hardware Allocation of -Packet
Buffer for Virtual Endpoints
- Multiple Virtual Endpoints (up to 16 TX, 16
RX Simultaneously)
- Multiple Alternate Address Filters
- Dynamic Endpoint Buffer Length
Allocation (0-1280 Byte Packets)
High Speed (12Mbps) Capability
MMU and SRAM Buffer Allow Buffer Optimization
and Maximum Utilization of USB Bandwidth
- 128 Byte Page Size
- 10 Pages Maximum per Packet
- Up to 16 Deep Receive Packet Queue
- Up to 5 Deep Transmit Packet Queue, per
Endpoint
- Hardware Generated Packet Header
Records Each Packet Status Automatically
- Simultaneous Arbitration Between MCU,
SIE, and ISA DMA Accesses
Extended Power Management
- Standard 8051 "Stop Clock" Modes
- Additional USB and ISA Suspend
Resume Events
- Internal 8MHz Ring Oscillator for Immediate
Low Power Code Execution
- 24, 16, 12, 8, 4, and 2 MHz PLL Taps For on
the Fly MCU and DMA Clock Switching
- Independent Clock/Power Management for
SIE, MMU, DMA and MCU
DMA Capability with ISA Memory
- Four Independent Channels
- Transfer Between Internal and External
Memory
- Transfer Between I/O and Buffer Memory
- External Bus Master Capable
External MCU Memory Interface
- 1M Byte Code and Data Storage via 16K
Windows
- Flash, SRAM, or EPROM
- Downloadable via USB, Serial Port, or ISA
Peripheral
Quasi-ISA Interface Allows Interface to New and
"Legacy" Peripheral Devices
- 1M ISA Memory Space via 4K MCU Window
- 64K ISA I/O Space via 256 Byte MCU
Window
- 4 External Interrupt Inputs
- 4 DMA Channels
- Variable Cycle Timing
- 8 Bit Data Path
5V or 3.3v Operation
On Board Crystal Driver Circuit
128 Pin QFP Package
ORDERING INFORMATION
Order Number: USB97C100QFP
128 Pin QFP Package
SMSC DS – USB97C100
Rev. 01/03/2001

1 Page





USB97C100 pdf, ピン配列
TABLE OF CONTENTS
FEATURES ................................................................................................................................................................... 1
GENERAL DESCRIPTION............................................................................................................................................ 2
PIN CONFIGURATION ................................................................................................................................................. 4
DESCRIPTION OF PIN FUNCTIONS ........................................................................................................................... 5
BUFFER TYPE DESCRIPTIONS.................................................................................................................................. 7
FUNCTIONAL DESCRIPTION...................................................................................................................................... 9
Serial Interface Engine (SIE)......................................................................................................................................... 9
Micro Controller Unit (MCU) .......................................................................................................................................... 9
SIEDMA......................................................................................................................................................................... 9
Memory Management Unit (MMU) Register Description ............................................................................................... 9
ISADMA......................................................................................................................................................................... 9
Applications ................................................................................................................................................................. 10
TYPICAL SIGNAL CONNECTIONS ............................................................................................................................ 12
MCU MEMORY MAP .................................................................................................................................................. 13
Code Space................................................................................................................................................................. 13
Data Space.................................................................................................................................................................. 13
ISADMA Memory Map ................................................................................................................................................. 13
MCU Block Register Summary.................................................................................................................................... 14
MMU Block Register Summary ................................................................................................................................... 15
SIE Block Register Summary ...................................................................................................................................... 16
MCU REGISTER DESCRIPTION................................................................................................................................ 17
MCU Runtime Registers.............................................................................................................................................. 17
FIFO Status Registers................................................................................................................................................. 20
MCU Power Management Registers ........................................................................................................................... 24
MCU ISA Interface Registers ...................................................................................................................................... 27
8237 (ISADMA) REGISTER DESCRIPTION .............................................................................................................. 30
Memory Map................................................................................................................................................................ 30
Runtime Registers....................................................................................................................................................... 31
MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION ....................................................................... 37
MMU Interface Registers............................................................................................................................................. 37
MMU FREE PAGES REGISTER................................................................................................................................. 40
16 BYTE DEEP TX COMPLETION FIFO REGISTER ................................................................................................ 40
TX FIFO POP REGISTER........................................................................................................................................... 41
SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION ............................................................................. 45
Packet Header Definition............................................................................................................................................. 45
SIE Interface Registers ............................................................................................................................................... 46
DC PARAMETERS ..................................................................................................................................................... 51
USB PARAMETERS ................................................................................................................................................... 53
USB DC PARAMETERS ............................................................................................................................................. 53
USB AC PARAMETERS.............................................................................................................................................. 54
MECHANICAL OUTLINE............................................................................................................................................ 63
USB97C100 REVISIONS............................................................................................................................................ 64
SMSC DS – USB97C100
Page 3
Rev. 01/03/2001


3Pages


USB97C100 電子部品, 半導体
QFP PIN
NUMBER
102
SYMBOL
nMASTER
21-24 IRQ[3:0]
30 XTAL1/
Clock In
31 XTAL2
99 EXTCLK
33 CLKOUT
77, 79
USBD-
USDB+
45-52 FD[7:0]
75, 74, 68,
65, 64, 69,
70, 63, 73,
43, 72, 71,
62-58,
56-54
42
66
44
98
FA[19:0]
nFRD
nFWR
nFCE
FALE
25,57,76
101,121
78
8, 20, 32,
53, 67, 80,
97, 116
VCC
VCC3.3
GND
41-34 GPIO[7:0]
PIN DESCRIPTION
External Bus master, active low
This signal forces the USB97C100 to immediately tri-state its
external bus, even if internal transactions are not complete. All
shared ISA signals are tri-stated, except 8237 nDACKs, which
can be used in gang mode to provide external bus-master
handshaking. This pin must be used with some handshake
mechanism to avoid data corruption.
Interrupt Request 3-0; active high
These signals are driven by ISA devices on the ISA bus to
interrupt the 8051.
24MHz Crystal or clock input.
This pin can be connected to one terminal of the crystal or can
be connected to an external clock when a crystal is not used.
24MHz Crystal
This is the other terminal of the crystal.
Alternate clock to 8237
An external clock can be used for the internal 8237. This clock
can be used to synchronize the 8237 to other devices.
Clock output.
This clock frequency is the same as the 8051 running clock.
This clock is stopped when the 8051 is stopped. Peripherals
should not use this clock when they are expected to run when
the 8051 is stopped. This clock can be used to synchronize
other devices to the 8051.
USB INTERFACE
USB Upstream Connection signals
These are two point-to-point signals and driven differentially.
FLASH INTERFACE
Flash ROM Data Bus
These signals are used to transfer data between 8051 and the
external FLASH.
Flash ROM Address Bus
These signals address memory locations within the FLASH.
Flash ROM Read; active low
Flash ROM Write; active low
Flash ROM Chip Select; active low
Flash ROM address latch enable
POWER SIGNALS
+3.3V power or 5V
+3.3V power for USB
Ground Reference
MISCELLANEOUS
General Purpose I/O.
These pins can be configured as inputs or outputs under
software control.
BUFFER
TYPE
IP
I
ICLKx
OCLKx
ICLK
O8
IO-U
IO8
O8
O8
O8
O8
O8
I/O16
SMSC DS – USB97C100
Page 6
Rev. 01/03/2001

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
USB97C100

Multi-Endpoint USB Peripheral Controller

SMSC Corporation
SMSC Corporation
USB97C102

Multi-Endpoint USB Peripheral Controller

SMSC Corporation
SMSC Corporation


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