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PDF AM186ED Data sheet ( Hoja de datos )
| Número de pieza | AM186ED | |
| Descripción | 16-Bit Embedded Microcontrollers | |
| Fabricantes | AMD | |
| Logotipo |  |
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PRELIMINARY
Am186TMED/EDLV
High Performance, 80C186- and 80C188-Compatible,
16-Bit Embedded Microcontrollers
DISTINCTIVE CHARACTERISTICS
n E86TM family 80C186- and 80C188-compatible
microcontroller with enhanced bus interface
– Serial port hardware handshaking with CTS,
RTS, ENRX, and RTR selectable for each port
– Lower system cost with higher performance
– 3.3-V ± 0.3-V operation (Am186EDLV
microcontrollers)
– Improved serial port operation enhances 9-bit
DMA support
– Independent serial port baud rate generators
n Programmable DRAM Controller
– DMA to and from the serial ports
– Supports zero-wait-state operation with 50-ns
– Watchdog timer can generate NMI or reset
DRAM at 40 MHz, 60-ns @ 33 MHz, 70-ns @ 25
MHz
– Includes programmable CAS-before-RAS
refresh capability
n High performance
– 20-, 25-, 33-, and 40-MHz operating frequencies
– Zero-wait-state operation at 40 MHz with 70-ns
static memory
T– 1-Mbyte memory address space
– 64-Kbyte I/O space
n Enhanced features provide improved memory
access and remove the requirement for a 2x clock
Fwww.DataSheet4U.com
input
– Nonmultiplexed address bus
– Processor operates at the clock input frequency
– 8-bit or 16-bit programmable bus sizing including
8-bit boot option
An Enhanced integrated peripherals
– 32 programmable I/O (PIO) pins
– Two full-featured asynchronous serial ports allow
full-duplex, 7-bit, 8-bit, or 9-bit data transfers
– A pulse-width demodulation option
– A data strobe, true asynchronous bus interface
option included for DEN
– Reset configuration register
n Familiar 80C186 peripherals
– Two independent DMA channels
– Programmable interrupt controller with up to 8 ex-
ternal and 8 internal interrupts
– Three programmable 16-bit timers
– Programmable memory and peripheral
chip-select logic
– Programmable wait state generator
– Power-save clock divider
n Software-compatible with the 80C186 and
80C188 microcontrollers with widely available
native development tools, applications, and
system software
n A compatible evolution of the Am186EM,
Am186ES, and Am186ER microcontrollers
n Available in the following packages:
– 100-pin, thin quad flat pack (TQFP)
– 100-pin, plastic quad flat pack (PQFP)
RGENERAL DESCRIPTION
The Am186TMED/EDLV microcontrollers are part of the
DAMD E86TM family of embedded microcontrollers and mi-
sizing, and programmable I/O (PIO) pins on one chip.
Compared to the 80C186/188 microcontrollers, the
croprocessors based on the x86 architecture. The Am186ED/EDLV microcontrollers enable designers to
Am186ED/EDLV microcontrollers are the ideal upgrade reduce the size, power consumption, and cost of em-
for 80C186/188 designs requiring 80C186/188 compat- bedded systems, while increasing reliability, functional-
ibility, increased performance, serial communications, a ity, and performance.
direct bus interface, and more than 64K of memory.
The Am186ED/EDLV microcontrollers have been
The Am186ED/EDLV microcontrollers integrate a com-
plete DRAM controller to take advantage of low DRAM
costs. This reduces memory subsystem costs while
maintaining SRAM performance.The Am186ED/EDLV
microcontrollers also integrate the functions of a CPU,
nonmultiplexed address bus, three timers, watchdog
timer, chip selects, interrupt controller, two DMA control-
designed to meet the most common requirements of
embedded products developed for the communications,
office automation, mass storage, and general
embedded markets. Specific applications include
PBXs, multiplexers, modems, disk drives, hand-held
and desktop terminals, fax machines, printers,
photocopiers, and industrial controls.
lers, two asynchronous serial ports, programmable bus
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices,
Inc.
Publication# 21336 Rev: A Amendment/0
Issue Date: May 1997
1 page  
PRELIMINARY
INT2/INTA0/PWD/PIO31 ................................................................................................ 24
INT3/INTA1/IRQ ............................................................................................................. 24
INT4/PIO30 .................................................................................................................... 25
LCS/ONCE0/RAS0 ........................................................................................................ 25
MCS0/PIO14 .................................................................................................................. 25
MCS1/UCAS/PIO15 ....................................................................................................... 25
MCS2/LCAS/PIO24 ....................................................................................................... 25
MCS3/RAS1/PIO25 ....................................................................................................... 26
NMI ................................................................................................................................ 26
PCS1/PIO17, PCS0/PIO16 ............................................................................................ 26
PCS2/CTS1/ENRX1/PIO18 ........................................................................................... 27
PCS3/RTS1/RTR1/PIO19 .............................................................................................. 27
PCS5/A1/PIO3 ............................................................................................................... 27
PCS6/A2/PIO2 ............................................................................................................... 28
PIO31–PIO0 (Shared) .................................................................................................... 28
RD .................................................................................................................................. 28
RES ................................................................................................................................ 28
RTS0/RTR0/PIO20 ........................................................................................................ 30
RXD0/PIO23 .................................................................................................................. 30
RXD1/PIO28 .................................................................................................................. 30
S2/BTSEL ...................................................................................................................... 30
S1–S0 ............................................................................................................................ 30
TS6/CLKDIV2/PIO29 ....................................................................................................... 30
SRDY/PIO6 .................................................................................................................... 30
TMRIN0/PIO11 ............................................................................................................... 31
TMRIN1/PIO0 ................................................................................................................ 31
FTMROUT0/PIO10 .......................................................................................................... 31
TMROUT1/PIO1 ............................................................................................................ 31
TXD0/PIO22 ................................................................................................................... 31
TXD1/PIO27 ................................................................................................................... 31
UCS/ONCE1 .................................................................................................................. 31
AUZI/PIO26 ...................................................................................................................... 31
VCC ................................................................................................................................ 31
WHB ............................................................................................................................... 31
WLB ............................................................................................................................... 32
RWR ................................................................................................................................. 32
X1 ................................................................................................................................... 32
X2 ................................................................................................................................... 32
FUNCTIONAL DESCRIPTION .................................................................................................. 33
DMemory Organization ..................................................................................................... 33
I/O Space ....................................................................................................................... 33
BUS OPERATION ..................................................................................................................... 34
BUS INTERFACE UNIT ............................................................................................................. 36
Nonmultiplexed Address Bus ......................................................................................... 36
DRAM Address Multiplexing .......................................................................................... 36
Programmable Bus Sizing ............................................................................................. 37
Byte-Write Enables ........................................................................................................ 37
Data Strobe Bus Interface Option .................................................................................. 37
DRAM INTERFACE ................................................................................................................... 37
PERIPHERAL CONTROL BLOCK ............................................................................................ 38
Reading and Writing the PCB ........................................................................................ 38
Am186ED/EDLV Microcontrollers
5
5 Page 
PRELIMINARY
n Enhanced performance—The Am186ED/EDLV
microcontrollers increase the performance of
80C186/188 systems, and the nonmultiplexed ad-
dress bus offers unbuffered access to memory.
n Enhanced functionality—The enhanced on-chip
peripherals of the Am186ED/EDLV microcontrollers
include two asynchronous serial ports, 32 PIOs, a
watchdog timer, additional interrupt pins, a pulse
width demodulation option, DMA directly to and from
the serial ports, 8-bit and 16-bit programmable bus
sizing, a 16-bit reset configuration register, and en-
hanced chip-select functionality.
Clock Generation
The integrated clock generation circuitry of the
Am186ED/EDLV microcontrollers enables the use of a
1x crystal frequency. The Am186ED design in Figure 1
achieves 40-MHz CPU operation, while using a 40-
MHz crystal.
Application Considerations
The integration enhancements of the Am186ED/EDLV
microcontrollers provide a high-performance, low-sys-
tem-cost solution for 16-bit embedded microcontroller
designs. The nonmultiplexed address bus eliminates
the need for system-support logic to interface memory
devices, while the multiplexed address/data bus main-
tains the value of previously engineered, customer-
specific peripherals and circuits within the upgraded
design.
Figure 1 illustrates an example system design that
Tuses the integrated peripheral set to achieve high per-
formance with reduced system cost.
Memory Interface
FThe Am186ED/EDLV microcontrollers integrate a ver-
satile memory controller which supports direct memory
accesses to DRAM, SRAM, Flash, EPROM, and ROM.
No external glue logic is required and all required con-
trol signals are provided. The peripheral chip selects
Ahave been enhanced to allow them to overlap the
DRAM. This allows a small 1.5K portion of the DRAM
memory space to be used for peripherals without bus
contention.
RThe improved memory timing specifications of the
Am186ED/EDLV microcontrollers allow for zero-wait-
state operation at 40 MHz using 50-ns DRAM, 70-ns
SRAM, or 70-ns Flash memory. For 60-ns DRAM one
wait state is required at 40 MHz and zero wait states at
D33 MHz and below. For 70-ns DRAM two wait states
0-6
Figure 1. Am186ED Microcontroller Example
System Design
Direct Memory Interface Example
Figure 1 illustrates the direct memory interface of the
Am186ED microcontroller. The processor’s A19–A0
bus connects to the memory address inputs, the AD
bus connects to the data inputs and outputs, and the
chip selects connect to the memory chip-select inputs.
The odd A1–A17 address pins connect to the DRAM
are required at 40 MHz, one wait state at 33 MHz, and
multiplexed address bus.
zero wait states at 25 MHz and below. This reduces The RD output connects to the DRAM Output Enable
overall system cost by enabling the use of commonly (OE) pin for read operations. Write operations use the
available memory speeds and taking advantage of WR output connected to the DRAM Write Enable (WE)
DRAM’s lower cost per bit over SRAM.
pin. The UCAS and LCAS pins provide byte selection.
Figure 1 also shows an implementation of an RS-232
console or modem communications port. The RS-232
to CMOS voltage-level converter is required for the
electrical interface with the external device.
Am186ED/EDLV Microcontrollers
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM186ED.PDF ] | |
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