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PDF CA3310A Data sheet ( 特性 )

部品番号 CA3310A
部品説明 A/D Converters
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 

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CA3310A Datasheet, CA3310A PDF,ピン配置, 機能
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CA3310, CA3310A
May 2001
File Number 3095.3
CMOS, 10-Bit, A/D Converters with
Internal Track and Hold
The Intersil CA3310 is a fast, low power, 10-bit successive
approximation analog-to-digital converter, with
microprocessor-compatible outputs. It uses only a single 3V
to 6V supply and typically draws just 3mA when operating at
5V. It can accept full rail-to-rail input signals, and features a
built-in track and hold. The track and hold will follow high
bandwidth input signals, as it has only a 100ns (typical) input
time constant.
The ten data outputs feature full high-speed CMOS three-
state bus driver capability, and are latched and held through
a full conversion cycle. Separate 8 MSB and 2 LSB enables,
a data ready flag, and conversion start and ready reset
inputs complete the microprocessor interface.
An internal, adjustable clock is provided and is available as
an output. The clock may also be driven from an external
source.
Part Number Information
PART LINEARITY
NUMBER (INL, DNL)
TEMP.
RANGE
(oC)
PACKAGE
PKG.
NO.
CA3310E ±0.75 LSB -40 to 85 24 Ld PDIP E24.6
CA3310M ±0.75 LSB -40 to 85 24 Ld SOIC M24.3
CA3310AM ±0.5 LSB -40 to 85 24 Ld SOIC M24.3
Features
• CMOS Low Power (Typ) . . . . . . . . . . . . . . . . . . . . . 15mW
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . 3V to 6V
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13µs
• Built-In Track and Hold
• Rail-to-Rail Input Range
• Latched Three-state Output Drivers
• Microprocessor-Compatible Control Lines
• Internal or External Clock
Applications
• Fast, No-Droop, Sample and Hold
• Voice Grade Digital Audio
• DSP Modems
• Remote Low Power Data Acquisition Systems
µP Controlled Systems
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Pinout
CA3310, CA3310A
(PDIP, SOIC)
TOP VIEW
D0 (LSB) 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
D8 9
D9 (MSB) 10
DRDY 11
VSS (GND) 12
24 VDD
23 VIN
22 VREF +
21 REXT
20 CLK
19 STRT
18 VREF -
17 VAA+
16 VAA-
15 OEL
14 OEM
13 DRST
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved

1 Page





CA3310A pdf, ピン配列
Typical Application Schematics
CA3310, CA3310A
8
ICL7663S
45
A
R2
+
VIN
-
A
R1
R4
-1V A
TO
-15V
4.7µF +
TAN
A
3 100Ω ±10%
1
6
ADJUST
GAIN
4.5V
75V
5K
4.7µF +
TAN
A
28.7K
A
A
R3 100
0.1
7
38
+
2 CA3140
6
-5
10K
41
+8V
TO
+15V
A
A
OPTIONAL
CLAMP
VDD
R5 47pF
0.1
ADJUST
OFFSET
100
VAA + VDD
VREF +
STRT
DRST
OEM
VREF -
OEL
CA3310/A
D0 - D9
VAA -
DRDY
CLK
REXT
VIN VSS
AD
D
+5V SUPPLY
0.1µF CER
D
START CONVERSATION
RESET FLAG
HIGH BYTE ENABLE
LOW BYTE ENABLE
OUTPUT DATA
DATA READY FLAG
2MHz CLOCK
NC
UNLESS NOTED,
ALL RESISTORS =
1% METAL FILM,
POTS = 10 TURN, CERMET
D = DIGITAL GROUND
A = ANALOG GROUND
INPUT RANGE
0V To 2.5V
0V To 5V
0V To 10V
-2.5V To +2.5V
-5V To +5V
R1
4.99K
4.99K
10K
4.99K
10K
R2
9.09K
4.53K
4.53K
9.09K
9.09K
R3
OPEN
OPEN
OPEN
9.09K
9.09K
R4
4.99K
4.99K
10K
4.99K
10K
R5
9.09K
4.53K
4.53K
4.53K
4.53K
3


3Pages


CA3310A 電子部品, 半導体
CA3310, CA3310A
Timing Diagrams
CLK
tD1 DRDY
DRDY
D0 - D9
INPUT
1 2 3 4 5 - 12 13
tD2 DRDY
tHIGH
tD DATA
DATA N - 1
TRACK N
HOLD
123
tLOW
DATA N
TRACK N + 1
tD APR
FIGURE 1. FREE RUNNING, STRT TIED LOW, DRST TIED HIGH
OEL OR OEM
D0 - D1 OR
D2- D9
OFF TO HIGH
OFF TO LOW
tEN
50%
50%
tDIS
90%
ZL = 50pF TO GND
1kTO GND
TO OUTPUT PIN
10%
ZL = 50pF TO GND
1kTO VDD
FIGURE 2. OUTPUT ENABLE/DISABLE TIMING DIAGRAM
13 1
CLK
(INTERNAL)
tR STRT
STRT
DRDY
INPUT
HOLD
2
TRACK
345
tD CLK
tW STRT
DON’T CARE
tD3 DRDY
HOLD
FIGURE 3. STRT PULSED LOW, DRST TIED HIGH, INTERNAL CLOCK
6

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