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HI5812 の電気的特性と機能

HI5812のメーカーはIntersil Corporationです、この部品の機能は「Sampling A/D Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 HI5812
部品説明 Sampling A/D Converter
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HI5812 Datasheet, HI5812 PDF,ピン配置, 機能
Semiconductor
HI5812
August 1997
CMOS 20 Microsecond, 12-Bit, Sampling A/D
Converter with Internal Track and Hold
Features
Description
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 20µs
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .50 KSPS
• Built-In Track and Hold
• Guaranteed No Missing Codes Over Temperature
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V
• Maximum Power Consumption. . . . . . . . . . . . . . .25mW
• Internal or External Clock
The HI5812 is a fast, low power, 12-bit, successive
approximation analog-to-digital converter. It can operate from
a single 3V to 6V supply and typically draws just 1.9mA when
operating at 5V. The HI5812 features a built-in track and hold.
The conversion time is as low as 15µs with a 5V supply.
The twelve data outputs feature full high speed CMOS three-
state bus driver capability, and are latched and held through a
full conversion cycle. The output is user selectable: (i.e.) 12-
bit, 8-bit (MSBs), and/or 4-bit (LSBs). A data ready flag, and
conversion-start inputs complete the digital interface.
Applications
• Remote Low Power Data Acquisition Systems
• Digital Audio
• DSP Modems
• General Purpose DSP Front End
µP Controlled Measurement System
• Professional Audio Positioner/Fader
An internal clock is provided and is available as an output.
The clock may also be over-driven by an external source.
Ordering Information
PART
NUMBER
HI5812JIP
HI5812KIP
HI5812JIB
HI5812KIB
HI5812JIJ
HI5812KIJ
INL (LSB)
(MAX OVER
TEMP.)
TEMP.
RANGE
(oC)
PACKAGE
PKG.
NO.
±1.5 -40 to 85 24 Ld PDIP E24.3
±1.0 -40 to 85 24 Ld PDIP E24.3
±1.5 -40 to 85 24 Ld SOIC M24.3
±1.0 -40 to 85 24 Ld SOIC M24.3
±1.5 -40 to 85 24 Ld CERDIP F24.3
±1.0 -40 to 85 24 Ld CERDIP F24.3
Pinout
HI5812
(PDIP, CERDIP, SOIC)
TOP VIEW
DRDY 1
(LSB) D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
D8 10
D9 11
VSS 12
24 VDD
23 OEL
22 CLK
21 STRT
20 VREF-
19 VREF+
18 VIN
17 VAA+
16 VAA-
15 OEM
14 D11 (MSB)
13 D10
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
6-1789
File Number 3214.4

1 Page





HI5812 pdf, ピン配列
HI5812
Absolute Maximum Ratings
Thermal Information
Supply Voltage
VDD to VSS . . . . . . . . . . . . . . . . . . . . (VSS -0.5V) < VDD < +6.5V
VAA+ to VAA-. . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V)
VAA+ to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
Analog and Reference Inputs
VIN, VREF+, VREF-. . . . . . . . . (VSS -0.3V) < VINA < (VDD +0.3V)
Digital I/O Pins . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD +0.3V)
Operating Conditions
Temperature Range
PDIP, SOIC, and CERDIP Packages . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . .
60
12
PDIP Package . . . . . . . . . . . . . . . . . . .
80
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
75
N/A
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Maximum Storage Temperature Range . . . . . . . . . .-65οC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF- = GND, CLK = External 750kHz,
Unless Otherwise Specified
25oC
-40oC TO 85oC
PARAMETER
ACCURACY
Resolution
Integral Linearity Error, INL
(End Point)
Differential Linearity Error, DNL
Gain Error, FSE
(Adjustable to Zero)
Offset Error, VOS
(Adjustable to Zero)
Power Supply Rejection, PSRR
Offset Error PSRR
Gain Error PSRR
DYNAMIC CHARACTERISTICS
Signal to Noise Ratio, SINAD
RMS Signal
RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
RMS Noise
Total Harmonic Distortion, THD
Spurious Free Dynamic Range,
SFDR
TEST CONDITIONS
MIN TYP MAX MIN
J
K
J
K
J
K
J
K
VREF = 4V
VDD = VAA+ = 5V ±5%
VDD = VAA+ = 5V ±5%
12 -
-
- - ±1.5
- - ±1.0
- - ±2.0
- - ±1.0
- - ±3.0
- - ±2.5
- - ±2.0
- - ±1.0
0.1 ±0.5
0.1 ±0.5
J fS = Internal Clock, fIN = 1kHz - 68.8 -
fS = 750kHz, fIN = 1kHz
69.2
K fS = Internal Clock, fIN = 1kHz - 71.0 -
fS = 750kHz, fIN = 1kHz
71.5
J fS = Internal Clock, fIN = 1kHz - 70.5 -
fS = 750kHz, fIN = 1kHz
71.1
K fS = Internal Clock, fIN = 1kHz - 71.5 -
fS = 750kHz, fIN = 1kHz
72.1
J fS = Internal Clock, fIN = 1kHz - -73.9 -
fS = 750kHz, fIN = 1kHz
-73.8
K fS = Internal Clock, fIN = 1kHz
fS = 750kHz, fIN = 1kHz
-80.3
-79.0
-
J fS =Internal Clock, fIN = 1kHz
fS = 750kHz, fIN = 1kHz
- -75.4 -
-75.1
K fS = Internal Clock, fIN = 1kHz - -80.9 -
fS = 750kHz, fIN = 1kHz
-79.6
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX UNITS
- Bits
±1.5 LSB
±1.0 LSB
±2.0 LSB
±1.0 LSB
±3.0 LSB
±2.5 LSB
±2.0 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
- dB
dB
- dB
dB
- dB
dB
- dB
dB
- dBc
dBc
- dBc
dBc
- dB
dB
- dB
dB
6-1791


3Pages


HI5812 電子部品, 半導体
Timing Diagrams (Continued)
HI5812
CLK
(INTERNAL)
STRT
DRDY
VIN
15 1
tRSTRT
2
3 45
tDSTRT
tWSTRT
DON’T CARE
tD3DRDY
HOLD
TRACK
FIGURE 3. SINGLE SHOT MODE INTERNAL CLOCK
HOLD
OEL OR OEM
tEN
D0 - D3 OR D4 - D11
HIGH IMPEDANCE
TO HIGH
HIGH
IMPEDANCE
TO LOW
50%
50%
tDIS
90%
TO
OUTPUT
PIN
50pF
10%
FIGURE 4A.
FIGURE 4. OUTPUT ENABLE/DISABLE TIMING DIAGRAM
1.6mA
+2.1V
-1.6mA
FIGURE 4B.
1.6mA
50pF
+2.1V
-400µA
FIGURE 5. GENERAL TIMING LOAD CIRCUIT
6-1794

6 Page



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