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SY89847U の電気的特性と機能

SY89847UのメーカーはMicrel Semiconductorです、この部品の機能は「LVDS 1:5 Fanout」です。


製品の詳細 ( Datasheet PDF )

部品番号 SY89847U
部品説明 LVDS 1:5 Fanout
メーカ Micrel Semiconductor
ロゴ Micrel Semiconductor ロゴ 




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SY89847U Datasheet, SY89847U PDF,ピン配置, 機能
SY89847U
1.5GHz Precision, LVDS 1:5 Fanout with 2:1
MUX and Fail Safe Input with Internal
Termination
General Description
The SY89847U is a 2.5V, 1:5 LVDS fanout buffer
with a 2:1 differential input multiplexer (MUX). A
unique Fail-Safe Input (FSI) protection prevents
metastable output conditions when the selected
Features
Precision Edge®
input clock fails to a DC voltage (voltage between Selects between two sources, and provides 5
the pins of the differential input drops significantly
precision LVDS copies
below 100mV).
Fail-Safe Input
The differential input includes Micrel’s unique, 3-pin
– Prevents outputs from oscillating when input is
internal termination architecture that can interface to
invalid
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Functional Block Diagram
Unique, patented internal termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
Wide input voltage range VCC to GND
2.5V ±5% supply voltage
-40°C to +85°C industrial temperature range
Available in 32-pin (5mm x 5mm) MLF® package
Applications
Fail-safe clock protection
Ultra-low jitter LVDS clock distribution
Rack-based Telecom/Datacom
Markets
LAN/WAN
Enterprise servers
ATE
Test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 2007
M9999-031307-A
[email protected] or (408) 955-1690

1 Page





SY89847U pdf, ピン配列
Micrel, Inc.
SY89847U
Pin Description
Pin Number
1, 8
2, 3
6, 7
10, 11, 30, 31
4
5
9, 32
12, 13, 16, 19,
22, 25, 28, 29
27, 26
24, 23
21, 20
18, 17
15, 14
Pin Name
VT0, VT1
IN0, /IN0
IN1, /IN1
GND,
Exposed Pad
OE
SEL
VREF-AC1
VREF-AC0
VCC
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Pin Function
Input Termination Center-Tap: Each side of a differential input pair terminates to
the VT pin. The VT pin provides a center-tap for each input (IN, /IN) to a
termination network for maximum interface flexibility. See “Input Interface
Applications” subsection.
Differential Inputs: These input pairs are the differential signal inputs to the
device. These inputs accept AC- or DC-coupled signals as small as 100mV. The
input pairs internally terminate to a VT pin through 50. Each input has level
shifting resistors of 3.72kto VCC. This allows a wide input voltage range from
VCC to GND. See Figure 3, Simplified Differential Input Stage for details. Note
that these inputs will default to a valid (either HIGH or LOW) state if left open.
See “Input Interface Applications” subsection.
Ground. Exposed pad must be connected to a ground plane that is the same
potential as the ground pins.
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q4
outputs. It is internally connected to a 25kpull-up resistor and will default to a
logic HIGH state if left open. When disabled, Q goes LOW and /Q goes HIGH.
OE being synchronous, outputs will be enabled/disabled following a rising and a
falling edge of the input clock. VTH = VCC/2.
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the
inputs to the multiplexer. Note that this input is internally connected to a 25k
pull-up resistor and will default to logic HIGH state if left open. VTH = VCC/2.
Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-
coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT
pin. Bypass with 0.01µF low ESR capacitor to VCC. Due to limited drive
capability, the VREF-AC pin is only intended to drive its respective VT pin.
Maximum sink/source current is ±0.5mA. See “Input Interface Applications”
subsection.
Positive Power Supply: Bypass with 0.1µF||0.01µF low ESR capacitors as close
to the VCC pins as possible.
LVDS Differential Output Pairs: Differential copies of the selected input signal.
The output swing is typically 325mV. Used and unused outputs must be
terminated with 100across the pair (Q, /Q). These differential LVDS outputs
are a logic function of the IN0, IN1, and SEL inputs. See “Truth Table” below.
Truth Table
Inputs
IN0 /IN0 IN1 /IN1 SEL
0 1XX0
1 0XX0
XX0 1 1
XX1 0 1
Outputs
Q /Q
01
10
01
10
March 2007
3 M9999-031307-A
[email protected] or (408) 955-1690


3Pages


SY89847U 電子部品, 半導体
Micrel, Inc.
SY89847U
AC Electrical Characteristics(8)
VCC = 2.5V ±5%, RL = 100across the outputs, Input tr/tf < 300ps; TA = –40°C to + 85°C, unless otherwise stated.
Symbol Parameter
fMAX Maximum Operating Frequency
tpd
tpd
Tempco
Differential Propagation Delay
IN-to-Q
IN-to-Q
SEL-to-Q
Differential Propagation Delay
Temperature Coefficient
Condition
VOUT > 200mV, VIN > 200mV
VOUT > 200mV, VIN > 100mV
Tpd varies with input tr/tf
100mV < VIN < 200mV, Note 9
200mV < VIN < 800mV, Note 9
VTH = VCC/2
Min Typ Max Units
1.5 2.0
GHz
1.0 1.5
GHz
600 820 1100 ps
500 720 1000 ps
400
600 800
ps
256 fs/oC
tSKEW
Output-to-Output Skew
Input-to-Input Skew
Note 11
Note 12
5 20 ps
5 15 ps
Part-to-Part Skew
Note 13
300 ps
tJITTER
tr, tf
Clock
Random Jitter
Cycle-to-Cycle Jitter
Total Jitter
Crosstalk-Induced Jitter
Output Rise/Fall Time (20% to 80%)
Duty Cycle
Note 14
Note 15
Note 16
Note 17
At full output swing.
VIN >200mV
100mV < VIN < 200mV
1 psRMS
1 psRMS
10 psPP
0.7 psRMS
70
120 210
ps
47 53 %
45 55
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9. Propagation delay is measured with input tr, tf 300ps (20% to 80%). The propagation delay is a function of the rise and fall times at IN.
See “Typical Operating Characteristics” for details.
10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set-up and hold do not apply.
11. Output-to-Output skew is measured between two different outputs under identical transitions.
12. Input-to-Input skew is the time difference between the two inputs to one output, under identical input transitions.
13. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs.
14. Random Jitter is measured with a K28.7 character pattern, measured at <fMAX.
15. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
16. Total Jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 1012 output edges will deviate by more
than the specified peak-to-peak jitter value.
17. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each
other at the inputs.
March 2007
6 M9999-031307-A
[email protected] or (408) 955-1690

6 Page



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部品番号部品説明メーカ
SY89847U

LVDS 1:5 Fanout

Micrel Semiconductor
Micrel Semiconductor


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