PDF ATAM894 Data sheet ( Hoja de datos )

Número de pieza	ATAM894
Descripción	8k-flash Microcontroller
Fabricantes	ATMEL Corporation
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No Preview Available ! Features • 8 K × 8-bit EEPROM • EEPROM Programmable Options • Read Protection for the EEPROM Program Memory • 256 × 4-bit RAM • 2 × 32 × 16-bit Data EEPROM • Up to Seven External/Internal Interrupt Sources • Eight Hardware and Software Interrupt Priorities • 16 Bi-directional I/Os • Wide Supply-voltage Range (1.8V to 6.5V) • Very Low Sleep Current (< 1 µA) • Synchronous Serial Interface (2-wire, 3-wire) • Multifunction Timer/Counter with Prescaler/Interval Timer • Voltage Monitoring Inclusive Lo_BAT Detect • Watchdog, POR and Brown-out Function 8k-flash Microcontroller ATAM894 1. Description The ATAM894 is a member of the Atmel’s family of 4-bit single chip microcontrollers with 8K × 8-bit EEPROM program memory. It is based on the 4-K MTP version ATAM893 and fully compatible with this MTP and the ROM versions ATAR090/890 and ATAR092/892. Figure 1-1. Block Diagram VSS VDD OSC1 OSC2 www.DataSheet4U.com BP10 BP13 BP20/NTE BP21 BP22 BP23 Brown-out protect. RESET Voltage monitor External input VMI Port 1 RC Crystal External oscillators oscillators clock input Clock management EEPROM RAM 8 K x 8 bit 256 x 4 bit MARC4 4-bit CPU core I/O bus UTCM Timer 1 interval- and watchdog timer Timer 2 with prescaler Modulator 2 SSI Serial interface Modulator 3 Demodulator Timer 3 timer/counter T2I T2O SD SC T3O T3I Data direction + alternate function Port 4 Data direction + interrupt control Port 5 Data dir. + alt. function Port 6 EEPROM 2 x 32 x 16 bit SD SC BP40 BP42 INT3 T2O SC BP41 BP43 VMI INT3 T2I SD BP50 INT6 BP52 INT1 BP51 INT6 BP53 INT1 BP60 BP63 T3O T3I Rev. 4679D–4BMCU–05/05 1 page ATAM894 5.2 Components of MARC4 Core The core contains ROM, RAM, ALU, program counter, RAM address registers, instruction decoder and interrupt controller. The following sections describe each functional block in more detail. 5.2.1 Program Memory The program memory (EEPROM) is electrically programmable and erasable with the customer application program. The program memory is addressed by a 12-bit wide program counter and an additional ROM bank register, thus predefining a maximum linear adressable program bank size of 4 Kbytes. The upper 2 Kbytes may be exchanged by ROM banking, thus allowing to address a maximum of 10 Kbytes user program. 8 Kbytes of program memory are available within the ATAM894. The lowest user (EEP)ROM address segment is taken up by a 512-byte zero page which contains predefined start addresses for interrupt service routines and special subroutines accessible with single byte instructions (SCALL). The corresponding memory map is shown in Figure 5-2. Look-up tables of constants can also be held in ROM and are accessed via the MARC4’s built-in table instruction. Figure 5-2. ROM Map Bank 4 Bank 3 Port D: 11xxb 1FFh FFFh Bank 2 Bank 1 Port D: 10xxb Port D: 01xxb 800h 7FFh Base bank 000h Zero page Port D: 00xxb 000h 1 F8 h 1F0h 1E8h 1E0h page 020h 018h 010h 008h 000h 1E0h 1C0h 180h 140h 100h 0C0h 080h 040h INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 008h 000h $RESET $AUTOSLEEP 5.2.1.1 ROM Banking For customers programming with qFORTH the bank switching is fully supported by the compiler. The MARC4 switches from one ROM bank to another by writing the new bank number to the ROM Bank Register (RBR). Conventional program space (power-up bank) resides in ROM bank 0. Each ROM bank consists of a 2 Kbyte address space whereby the lowest 2 Kbyte, the base bank, is common to all banks, so that addresses between 000h and 7FFh always access the same ROM data (see Figure 5-2). When ROM banking is used, the compiler will, if necessary, insert program code to save and restore the condition of the RBR on bank switching. 5.2.2 RAM The ATAM894 contains 256 × 4-bit wide static random access memory (RAM). It is used for the expression stack, the return stack and data memory for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y. 4679D–4BMCU–05/05 5 5 Page ATAM894 Table 5-1. Interrupt Priority Table Interrupt INT0 INT1 INT2 Priority Lowest \| \| ROM Address 040h 080h 0C0h INT3 \| 100h INT4 INT5 \| \| 140h 180h INT6 ↓ 1C0h INT7 Highest 1E0h Interrupt Opcode C8h (SCALL 040h) D0h (SCALL 080h) D8h (SCALL 0C0h) E8h (SCALL 100h) E8h (SCALL 140h) F0h (SCALL 180h) F8h (SCALL 1C0h) FCh (SCALL 1E0h) Function Software interrupt (SWI0) External hardware interrupt, any edge at BP52 or BP53 Timer 1 interrupt SSI interrupt or external hardware interrupt at BP40 or BP43 Timer 2 interrupt Timer 3 interrupt External hardware interrupt, at any edge at BP50 or BP51 Voltage Monitor (VM) interrupt Table 5-2. Hardware Interrupts Interrupt INT1 INT2 INT3 INT4 INT5 INT6 INT7 Interrupt Mask Register Bit P5CR P52M1, P52M2 P53M1, P53M2 T1M T1IM SISC SIM T2CM T2IM T3CM1 T3CM2 T3C T3IM1 T3IM2 T3EIM P5CR P50M1, P50M2 P51M1, P51M2 VCM VIM Interrupt Source Any edge at BP52 Any edge at BP53 Timer 1 SSI buffer full/empty or BP40/BP43 interrupt Timer 2 compare match/overflow Timer 3 compare register 1 match Timer 3 compare register 2 match Timer 3 edge event occurs (T3I) Any edge at BP50 Any edge at BP51 External/internal voltage monitoring 5.2.9.1 Software Interrupts The programmer can generate interrupts by using the software interrupt instruction (SWI) which is supported in qFORTH by predefined macros named SWI0 to SWI7. The software triggered interrupt operates exactly like any hardware triggered interrupt. The SWI instruction takes the top two elements from the expression stack and writes the corresponding bits via the I/O bus to the interrupt pending register. Therefore, by using the SWI instruction, interrupts can be re-prior- itized or lower priority processes scheduled for later execution. 5.2.9.2 Hardware Interrupts In the ATAM894, there are eleven hardware interrupt sources with seven different levels. Each source can be masked individually by mask bits in the corresponding control registers. An over- view of the possible hardware configurations is shown in Table 5-2 on page 11. 4679D–4BMCU–05/05 11 11 Page

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