PDF AT25DF041A Data sheet ( Hoja de datos )

Número de pieza	AT25DF041A
Descripción	4-megabit 2.7-volt Only Serial Firmware DataFlash Memory
Fabricantes	ATMEL Corporation
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Features • Single 2.7V - 3.6V Supply • Serial Peripheral Interface (SPI) Compatible – Supports SPI Modes 0 and 3 • 70 MHz Maximum Clock Frequency • Flexible, Uniform Erase Architecture – 4-Kbyte Blocks – 32-Kbyte Blocks – 64-Kbyte Blocks – Full Chip Erase • Individual Sector Protection with Global Protect/Unprotect Feature – One 16-Kbyte Top Boot Sector – Two 8-Kbyte Sectors – One 32-Kbyte Sector – Seven 64-Kbyte Sectors • Hardware Controlled Locking of Protected Sectors • Flexible Programming Options – Byte/Page Program (1 to 256 Bytes) – Sequential Program Mode Capability • Automatic Checking and Reporting of Erase/Program Failures • JEDEC Standard Manufacturer and Device ID Read Methodology • Low Power Dissipation – 5 mA Active Read Current (Typical) – 10 µA Deep Power-down Current (Typical) • Endurance: 100,000 Program/Erase Cycles • Data Retention: 20 Years www.DataSheet4U.com • Complies with Full Industrial Temperature Range • Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC (150-mil and 200-mil wide) – 8-contact MLF (5 x 6 mm) 4-megabit 2.7-volt Only Serial Firmware DataFlash® Memory AT25DF041A Preliminary 1. Description The AT25DF041A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer-based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DF041A, with its erase granularity as small as 4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. The physical sectoring and the erase block sizes of the AT25DF041A have been opti- mized to meet the needs of today’s code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows addi- tional code routines and data storage segments to be added while still maintaining the same overall device density. 3668A–DFLASH–03/07 1 page Figure 4-1. Memory Architecture Diagram Block Erase Detail Internal Sectoring for Sector Protection Function 16KB (Sector 10) 8KB (Sector 9) 8KB (Sector 8) 32KB (Sector 7) 64KB (Sector 6) 64KB 32KB 4KB Block Erase Block Erase Block Erase (D8h Command) (52h Command) (20h Command) Block Address Range 64KB 64KB 32KB 32KB 32KB 32KB 4KB 07F F F F h – 07F 000h 4KB 07E F F F h – 07E 000h 4KB 07DF F F h – 07D000h 4KB 07CF F F h – 07C000h 4KB 07BF F F h – 07B000h 4KB 07AF F F h – 07A000h 4KB 079F F F h – 079000h 4KB 078F F F h – 078000h 4KB 077F F F h – 077000h 4KB 076F F F h – 076000h 4KB 075F F F h – 075000h 4KB 074F F F h – 074000h 4KB 073F F F h – 073000h 4KB 072F F F h – 072000h 4KB 071F F F h – 071000h 4KB 070F F F h – 070000h 4KB 06F F F F h – 06F 000h 4KB 06E F F F h – 06E 000h 4KB 06DF F F h – 06D000h 4KB 06CF F F h – 06C000h 4KB 06BF F F h – 06B000h 4KB 06AF F F h – 06A000h 4KB 069F F F h – 069000h 4KB 068F F F h – 068000h 4KB 067F F F h – 067000h 4KB 066F F F h – 066000h 4KB 065F F F h – 065000h 4KB 064F F F h – 064000h 4KB 063F F F h – 063000h 4KB 062F F F h – 062000h 4KB 061F F F h – 061000h 4KB 060F F F h – 060000h 64KB (Sector 0) 64KB 32KB 32KB 4KB 00F F F F h – 00F 000h 4KB 00E F F F h – 00E 000h 4KB 00DF F F h – 00D000h 4KB 00CF F F h – 00C000h 4KB 00BF F F h – 00B000h 4KB 00AF F F h – 00A000h 4KB 009F F F h – 009000h 4KB 008F F F h – 008000h 4KB 007F F F h – 007000h 4KB 006F F F h – 006000h 4KB 005F F F h – 005000h 4KB 004F F F h – 004000h 4KB 003F F F h – 003000h 4KB 002F F F h – 002000h 4KB 001F F F h – 001000h 4KB 000F F F h – 000000h AT25DF041A Page Program Detail 1-256 Byte Page Program (02h Command) Page Address Range 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 07FFFFh – 07FF00h 07FEFFh – 07FE00h 07F DF F h – 07F D00h 07FCFFh – 07FC00h 07FBFFh – 07FB00h 07F AF F h – 07F A00h 07F9FFh – 07F900h 07F8FFh – 07F800h 07F7FFh – 07F700h 07F6FFh – 07F600h 07F5FFh – 07F500h 07F4FFh – 07F400h 07F3FFh – 07F300h 07F2FFh – 07F200h 07F1FFh – 07F100h 07F0FFh – 07F000h 07EFFFh – 07EF00h 07EEFFh – 07EE00h 07E DF F h – 07E D00h 07ECFFh – 07EC00h 07EBFFh – 07EB00h 07E AF F h – 07E A00h 07E9FFh – 07E900h 07E8FFh – 07E800h 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 0017FFh – 001700h 0016FFh – 001600h 0015FFh – 001500h 0014FFh – 001400h 0013FFh – 001300h 0012FFh – 001200h 0011FFh – 001100h 0010FFh – 001000h 000FFFh – 000F00h 000EFFh – 000E00h 000DF F h – 000D00h 000CFFh – 000C00h 000BFFh – 000B00h 000AF F h – 000A00h 0009FFh – 000900h 0008FFh – 000800h 0007FFh – 000700h 0006FFh – 000600h 0005FFh – 000500h 0004FFh – 000400h 0003FFh – 000300h 0002FFh – 000200h 0001FFh – 000100h 0000FFh – 000000h 3668A–DFLASH–03/07 5 5 Page AT25DF041A device. Deasserting the CS pin will start the internally self-timed program operation, and the byte of data will be programmed into the memory location specified by A23 - A0. After the first byte has been successfully programmed, a second byte can be programmed by simply reasserting the CS pin, clocking in the ADh or AFh opcode, and then clocking in the next byte of data. When the CS pin is deasserted, the second byte of data will be programmed into the next sequential memory location. The process would be repeated for any additional bytes. There is no need to reissue the Write Enable command once the Sequential Program Mode has been entered. When the last desired byte has been programmed into the memory array, the Sequential Program Mode operation can be terminated by reasserting the CS pin and sending the Write Disable command to the device to reset the WEL bit in the Status Register back to the logical “0” state. If more than one byte of data is ever clocked in during each program cycle, then only the last byte of data sent on the SI pin will be stored in the internal latches. The programming of each byte is internally self-timed and should take place in a time of tBP. For each program cycle, a complete byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the byte of data will not be programmed into the memory array, and the WEL bit in the Status Register will be reset back to the logical “0” state. If the address initially specified by A23 - A0 points to a memory location within a sector that is in the protected state, then the Sequential Program Mode command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Sta- tus Register will also be reset back to the logical “0” state. There is no address wrapping when using the Sequential Program Mode. Therefore, when the last byte (07FFFFh) of the memory array has been programmed, the device will automatically exit the Sequential Program mode and reset the WEL bit in the Status Register back to the logi- cal “0” state. In addition, the Sequential Program mode will not automatically skip over protected sectors; therefore, once the highest unprotected memory location in a programming sequence has been programmed, the device will automatically exit the Sequential Program mode and reset the WEL bit in the Status Register. For example, if Sector 1 was protected and Sector 0 was currently being programmed, once the last byte of Sector 0 was programmed, the Sequen- tial Program mode would automatically end. To continue programming with Sector 2, the Sequential Program mode would have to be restarted by supplying the ADh or AFh opcode, the three address bytes, and the first byte of Sector 2 to program. While the device is programming a byte, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled at the end of each program cycle rather than waiting the tBP time to determine if the byte has fin- ished programming before starting the next Sequential Program mode cycle. The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register. 3668A–DFLASH–03/07 11 11 Page

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