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PDF IRS20955PBF Data sheet ( Hoja de datos )
| Número de pieza | IRS20955PBF | |
| Descripción | PROTECTED DIGITAL AUDIO DRIVER | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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PRELIMINARY
Data Sheet No. PD60303
IRS20955(S)PbF
PROTECTED DIGITAL AUDIO DRIVER
Features
· Floating PWM input enables easy half-bridge
implementation
· Programmable bidirectional over-current protection
with self-reset function
· Programmable preset deadtime for improved THD
performances
· High noise immunity
· ±100 V ratings deliver up to 500 W in output power
· 3.3 V/5 V logic compatible input
· Operates up to 800 kHz
· RoHS compliant
Product Summary
VOFFSET (max)
Gate driver
Io+
Io-
Selectable deadtime
Propagation delay
OC protection delay
Shutdown propagation
delay
± 100 V
1.0 A
1.2 A
15 ns, 25 ns,
35 ns, 45ns
90 ns
500 ns (max)
250 ns (max)
Description
The IRS20955 is a high voltage, high speed MOSFET driver
with a floating PWM input designed for Class D audio
amplifier applications.
Package
Bi-directional current sensing detects over-current www.DataSheet4U.com
conditions during positive and negative load currents without
any external shunt resistors. A built-in protection control
block provides a secure protection sequence against over-
current conditions and a programmable reset timer.
The internal deadtime generation block enables accurate
gate switching and optimum deadtime setting for better
audio performance, such as lower THD and lower audio
noise floor.
16-Lead PDIP
16-Lead SOIC
Typical Connection
PWM
(Please refer to Lead
Assignments for correct
pin configuration. This
diagram shows
electrical connections
only)
www.irf.com
IRS20955 (S)
VDD
CSD
IN
VSS
NC
VREF
OCSET
DT
CSH
VB
HO
VS
NC
VCC
LO
COM
+B
Speaker
Vcc
12V
-B
1
1 page  
IRS20955(S)PbF
PRELIMINARY
Electrical Characteristics (cont.)
VCC ,VBS= 12 V, IDD=5 mA, VSS=20 V, VS=0 V,CL=1 nF and TA=25 °C unless otherwise specified.
VOH
tr
tf
ton,1
toff,1
ton,2
toff,2
DT1
DT2
DT3
DT4
VDT1
VDT2
VDT3
High level output voltage
VCC – LO, VB – HO
Turn-on rise time
Turn-off fall time
High-side and low-side turn-on
propagation delay, floating inputs
High-side and low-side turn-off
propagation delay, floating inputs
High-side and low-side turn-on
propagation delay, non-floating inputs
High-side and low-side turn-off
propagation delay, non-floating inputs
Deadtime: LO turn-off to HO turn-on
(DTLO-HO) & HO turn-off to LO turn-on
(DTHO-LO)
Deadtime: LO turn-off to HO turn-on
(DTLO-HO) & HO turn-off to LO turn-on
(DTHO-LO)
Deadtime: LO turn-off to HO turn-on
(DTLO-HO) & HO turn-off to LO turn-on
(DTHO-LO)
Deadtime: LO turn-off to HO turn-on
(DTLO-HO) & HO turn-off to LO turn-on
(DTHO-LO)VDT= VDT4
DT mode select threshold 2
DT mode select threshold 3
DT mode select threshold 4
--
- 15
- 10
- 105
- 90
- 105
- 90
8 15
15 25
20 35
25 45
0.51(V cc)
0.32(V cc)
0.21(V cc)
0.57(V cc)
0.36(V cc)
0.23(V cc)
1.4
-
-
-
-
-
-
22
35
50
60
0.63(V cc)
0.40(V cc)
0.25(V cc)
V
ns
V
IO=0 A
VDT = VCC,
VS = 100 V,
VSS = 100 V
VDT = VCC,
VS = 100V,
VSS = COM
VDT>VDT1,
VSS = COM
VDT1>VDT> VDT2,
VSS = COM
VDT2>VDT> VDT3,
VSS = COM
VDT3>VDT> VDT4,
VSS = COM
www.irf.com
5
5 Page 
Shutdown Input
When VCSD falls below Vth2, the IRS20955S begins
to charge Ct in an attempt to resume operation.
Once the voltage of the CSD pin rises above the
upper threshold, Vth1, the IC begins to operate
normally again.
SHUTDOWN
VDD
CSD
IN
VSS
NC
VREF
OCSET
DT
CSH
VB
HO
VS
NC
VCC
LO
COM
Figure 9. Shutdown Input
Latched Protection
Connecting CSD to VDD through a 10 kΩ or less
resistor configures the over current protection latch.
The latch locks the IC in shutdown mode after over
current is detected. An external reset switch can be
used to bring CSD below the lower threshold Vth2 for
a minimum of 200 ns to properly reset the latch.
After the power up sequence, a reset signal to the
CSD pin is required to release the IC from shutdown
mode.
RESET
<10k
VDD
CSD
IN
VSS
NC
VREF
OCSET
DT
CSH
VB
HO
VS
NC
VCC
LO
COM
Figure 10. Latched Protection Configuration
IRS20955(S)PbF
PRELIMINARY
Interfacing with System Controller
The IRS20955S can communicate with an external
system controller through a simple interfacing circuit
such as the one shown in Figure 11. A generic PNP
transistor, shown as U1, can detect the sink current
at the CSD pin during an OCP event and output a
shutdown signal to an external system controller.
Another generic NPN transistor, shown as U2, can
then reset the internal protection logic by pulling the
CSD voltage below Vth2 for a minimum of 200 ns.
Note that the CSD pin is configured to operate in
latched OCP. After the power up sequence, a reset
signal to the CSD pin is required to release the IC
from shutdown mode.
Figure 11. Interfacing with System Controller
Programming OCP Trip Level
In a Class D audio amplifier, the direction of the load
current alternates with the audio input signal. An
over-current condition can therefore occur during
either a positive current cycle or a negative current
cycle. The IRS20955 uses the RDS(ON) of the output
MOSFETs as current sensing resistors. Due to the
structural constraints of high voltage ICs, current
sensing is implemented differently for high side and
low side. If the measured current exceeds a
predetermined threshold, the OCP block outputs a
signal to the protection block to shutdown the
MOSFET to protect the switching devices.
www.irf.com
11
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| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet IRS20955PBF.PDF ] | |
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