DataSheet.jp

5962-8688001QA PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 5962-8688001QA
部品説明 CMOS ARINC Bus Interface Circuit
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 



Total 15 pages
		

No Preview Available !

5962-8688001QA Datasheet, 5962-8688001QA PDF,ピン配置, 機能
HS-3282
REFERENCE AN400
March 1997
CMOS ARINC Bus Interface Circuit
Features
Description
• ARlNC Specification 429 Compatible
The HS-3282 is a high performance CMOS bus interface
• Data Rates of 100 Kilobits or 12.5 Kilobits
circuit that is intended to meet the requirements of ARINC
Specification 429, and similar encoded, time multiplexed
• Separate Receiver and Transmitter Section
serial data protocols. This device is intended to be used with
• Dual and Independent Receivers, Connecting Directly
to ARINC Bus
the HS-3182, a monolithic Dl bipolar differential line driver
designed to meet the specifications of ARINC 429. The
ARINC 429 bus interface circuit consists of two (2) receivers
• Serial to Parallel Receiver Data Conversion
• Parallel to Serial Transmitter Data Conversion
and a transmitter operating independently as shown in
Figure 1. The two receivers operate at a frequency that is ten
(10) times the receiver data rate, which can be the same or
• Word Lengths of 25 or 32 Bits
• Parity Status of Received Data
different from the transmitter data rate. Although the two
receivers operate at the same frequency, they are
functionally independent and each receives serial data asyn-
• Generate Parity of Transmitter Data
chronously. The transmitter section of the ARINC bus
interface circuit consists mainly of a First-In First-Out (FIFO)
• Automatic Word Gap Timer
memory and timing circuit. The FIFO memory is used to hold
• Single 5V Supply
up to eight (8) ARINC data words for transmission serially.
The timing circuit is used to correctly separate each ARINC
• Low Power Dissipation
word as required by ARINC Specification 429. Even though
• Full Military Temperature Range
ARINC Specification 429 specifies a 32-bit word, including
parity, the HS-3282 can be programmed to also operate with
Ordering Information
a word length of 25 bits. The incoming receiver data word
paritywww.DataSheet4U.com is checked, and a parity status is stored in the receiver
PKG. latch and output on Pin BD08 during the 1st word. [A logic
PACKAGE TEMP. RANGE PART NUMBER NO.
“0” indicates that an odd number of logic “1” s were received
CERDIP
SMD#
CLCC
-55oC to +125oC HS1-3282-8
F40.6
5962-8688001QA F40.6
-40oC to +85oC HS4-3282-9+
J44.A
and stored; a logic “1” indicates that an even number of logic
“1”s were received and stored]. In the transmitter the parity
generator will generate either odd or even parity depending
upon the status of PARCK control signal. A logic “0” on BD12
-55oC to +125oC HS4-3282-8
J44.A
will cause odd parity to be used in the output data stream.
SMD#
5962-8688001XA J44.A
Versatility is provided in both the transmitter and receiver by
the external clock input which allows the bus interface circuit
to operate at data rates from 0 to 100 kilobits. The external
clock must be ten (10) times the data rate to insure no data
ambiguity.
The ARINC bus interface circuit is fully guaranteed to
support the data rates of ARINC specification 429 over both
the voltage (±5%) and full military temperature range. It
interfaces with UL, CMOS or NMOS support circuitry, and
uses the standard 5-volt VCC supply.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-183
File Number 2964.2

1 Page





ページ 合計 : 15 ページ
PDF
ダウンロード
[ 5962-8688001QA.PDF ]

共有リンク

Link :

おすすめデータシート

部品番号部品説明メーカ
5962-8688001QA

CMOS ARINC Bus Interface Circuit

Intersil Corporation
Intersil Corporation

www.DataSheet.jp    |   2019   |  メール    |   最新    |   Sitemap