|
|
PDF ISGAL22V10 Data sheet ( Hoja de datos )
| Número de pieza | ISGAL22V10 | |
| Descripción | In-System Programmable E2CMOS PLD | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISGAL22V10 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
SpecificatiiosnpsGispAGLA2L222VV1100
In-System Programmable E2CMOS PLD
Generic Array Logic™
FEATURES
FUNCTIONAL BLOCK DIAGRAM
• IN-SYSTEM PROGRAMMABLE™ (5-V ONLY)
— 4-Wire Serial Programming Interface
— Minimum 10,000 Program/Erase Cycles
— Built-in Pull-Down on SDI Pin Eliminates Discrete
Resistor on Board (ispGAL22V10C Only)
I/CLK
I
RESET
8
OLMC
I/O/Q
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
10
I
OLMC
I/O/Q
— Fmax = 111 MHz
12
— 5 ns Maximum from Clock Input to Data Output
I
OLMC
I/O/Q
— UltraMOS® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
I
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and CMOS 22V10 Devices
I
• E2 CELL TECHNOLOGY
— In-System Programmable Logic
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
I
I
I
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
I
• APPLICATIONS INCLUDE:
www.DataSheet4U.com
— DMA Control
— State Machine Control
I
— High Speed Graphics Processing
— Software-Driven Hardware Configuration
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
SDO
SDI
MODE
SCLK
I
PROGRAMMING
LOGIC
DESCRIPTION
The ispGAL22V10, at 7.5ns maximum propagation delay time,
PIN CONFIGURATION
combines a high performance CMOS process with Electrically
Erasable (E2) floating gate technology to provide the industry's
first in-system programmable 22V10 device. E2 technology of-
PLCC
fers high speed (<100ms) erase times, providing the ability to re-
program or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
4 2 28 26
I5
2 5 I/O/Q
the user. The ispGAL22V10 is fully function/fuse map/parametric
I
I/O/Q
compatible with standard bipolar and CMOS 22V10 devices. The
standard PLCC package provides the same functional pinout as
the standard 22V10 PLCC package with No-Connect pins being
used for the ISP interface signals.
I7
MODE
I9
ispGAL22V10
Top View
2 3 I/O/Q
SDO
2 1 I/O/Q
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
I
I 11 12
14 16
I/O/Q
1 8 1 9 I/O/Q
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 10,000 erase/write
cycles and data retention in excess of 20 years are specified.
14
OLMC
16
OLMC
16
OLMC
14
OLMC
12
OLMC
10
OLMC
8
OLMC
PRESET
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
SSOP
SCLK
I/CLK
I
I
I
I
I
MODE
I
I
I
I
I
GND
1 28
ispGAL
7 22V10 22
Top View
14 15
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
SDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
SDI
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
isp22v10_02
1
1 page  
Specifications ispGAL22V10
ispGAL22V10 LOGIC DIAGRAM / JEDEC FUSE MAP
PLCC & SSOP Package Pinout
2
0 4 8 12 16 20 24 28 32 36 40
0000
0044
.
.
.
0396
0440
.
.
.
.
0880
3
0924
.
.
.
.
.
1452
4
1496
.
.
.
.
.
.
2112
5
2156
.
.
.
.
.
.
.
2860
6
2904
.
.
.
.
.
.
.
3608
7
9
10
11
12
13
3652
.
.
.
.
.
.
4268
4312
.
.
.
.
.
4840
4884
.
.
.
.
5324
5368
.
.
.
5720
5764
5828, 5829 ... Electronic Signature ... 5890, 5891
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
ML
SS
BB
8
10
12
14
16
16
14
12
10
8
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
OLMC
S0
5808
S1
5809
27
OLMC
S0
5810
S1
5811
26
OLMC
S0
5812
S1
5813
25
OLMC
S0
5814
S1
5815
24
OLMC
S0
5816
S1
5817
23
OLMC
S0
5818
S1
5819
21
OLMC
S0
5820
S1
5821
20
OLMC
S0
5822
S1
5823
19
OLMC
S0
5824
S1
5825
18
OLMC
S0
5826
S1
5827
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
17
16
5
5 Page 
Specifications ispGAL22V10
POWER-UP RESET
V c c Vcc (min.)
CLK
INTERNAL REGISTER
Q - OUTPUT
t su
t wl
t pr
Internal Register
Reset to Logic "0"
ACTIVE LOW
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
ACTIVE HIGH
OUTPUT REGISTER
Device Pin
Reset to Logic "0"
Circuitry within the ispGAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1µs MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the ispGAL22V10.
First, the Vcc rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
PIN
(Vref Typical = 3.2V)
Active Pull-up
Circuit (Except SDI
on ispGAL22V10C)
Vcc
Vcc Vref Vcc
ESD
Protection
Circuit
PIN
Feedback
Tri-State
Control
Active Pull-up
Circuit
Vcc Vref
(Vref Typical = 3.2V)
PIN
ESD
Protection
Circuit
Pull-down Resistor
(SDI on ispGAL22V10C Only)
Input
Data
Output
PIN
Feedback
(To Input Buffer)
Output
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ISGAL22V10.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISGAL22V10 | In-System Programmable E2CMOS PLD | Lattice Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |