DataSheet.jp

MC33172 の電気的特性と機能

MC33172のメーカーはON Semiconductorです、この部品の機能は「(MC33171 - MC33174) Low Power Operational Amplifiers」です。


製品の詳細 ( Datasheet PDF )

部品番号 MC33172
部品説明 (MC33171 - MC33174) Low Power Operational Amplifiers
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 




このページの下部にプレビューとMC33172ダウンロード(pdfファイル)リンクがあります。

Total 15 pages

No Preview Available !

MC33172 Datasheet, MC33172 PDF,ピン配置, 機能
MC33171, 2, 4,
NCV33172, 4
Single Supply 3.0 V to 44 V,
Low Power Operational
Amplifiers
Quality bipolar fabrication with innovative design concepts are
employed for the MC33171/72/74, NCV33172/74 series of
monolithic operational amplifiers. These devices operate at 180 mA
per amplifier and offer 1.8 MHz of gain bandwidth product and
2.1 V/ms slew rate without the use of JFET device technology.
Although this series can be operated from split supplies, it is
particularly suited for single supply operation, since the common
mode input voltage includes ground potential (VEE). With a
Darlington input stage, these devices exhibit high input resistance, low
input offset voltage and high gain. The all NPN output stage,
characterized by no deadband crossover distortion and large output
voltage swing, provides high capacitance drive capability, excellent
phase and gain margins, low open loop high frequency output
impedance and symmetrical source/sink AC frequency response.
The MC33171/72/74, NCV33172/74 are specified over the
industrial/automotive temperature ranges. The complete series of
single, dual and quad operational amplifiers are available in plastic as
well as the surface mount packages.
Features
Low Supply Current: 180 mA (Per Amplifier)
Wide Supply Operating Range: 3.0 V to 44 V or ±1.5 V to ±22 V
Wide Input Common Mode Range, Including Ground (VEE)
Wide Bandwidth: 1.8 MHz
High Slew Rate: 2.1 V/ms
Low Input Offset Voltage: 2.0 mV
Large Output Voltage Swing: −14.2 V to +14.2 V
(with ±15 V Supplies)
Large Capacitance Drive Capability: 0 pF to 500 pF
Low Total Harmonic Distortion: 0.03%
Excellent Phase Margin: 60°
Excellent Gain Margin: 15 dB
Output Short Circuit Protection
ESD Diodes Provide Input Protection for Dual and Quad
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
www.onsemi.com
8
1
8
1
PDIP−8
P SUFFIX
CASE 626
SO−8
D, VD SUFFIX
CASE 751
14
1
14
1
14
1
PDIP−14
P, VP SUFFIX
CASE 646
SO−14
D, VD SUFFIX
CASE 751A
TSSOP−14
DTB SUFFIX
CASE 948G
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 13
1
Publication Order Number:
MC33171/D

1 Page





MC33172 pdf, ピン配列
MC33171, 2, 4, NCV33172, 4
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Supply Voltage
VCC/VEE
±22
V
Input Differential Voltage Range
VIDR
(Note 1)
V
Input Voltage Range
VIR (Note 1)
V
Output Short Circuit Duration (Note 2)
tSC Indefinite sec
Operating Ambient Temperature Range
TA (Note 3) °C
Operating Junction Temperature
TJ +150 °C
Storage Temperature Range
Tstg −65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, RL connected to ground, TA = +25°C, unless otherwise noted.)
Characteristics
Symbol Min Typ Max Unit
Input Offset Voltage (VCM = 0 V)
VCC = +15 V, VEE = −15 V, TA = +25°C
VCC = +5.0 V, VEE = 0 V, TA = +25°C
VCC = +15 V, VEE = −15 V, TA = Tlow to Thigh (Note 3)
Average Temperature Coefficient of Offset Voltage
Input Bias Current (VCM = 0 V)
TA = +25°C
TA = Tlow to Thigh (Note 3)
Input Offset Current (VCM = 0 V)
TA = +25°C
TA = Tlow to Thigh (Note 3)
Large Signal Voltage Gain (VO = ±10 V, RL = 10 k)
TA = +25°C
TA = Tlow to Thigh (Note 3)
Output Voltage Swing
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 k, TA = Tlow to Thigh (Note 3)
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = −15 V, RL = 10 k, TA = Tlow to Thigh (Note 3)
Output Short Circuit (TA = +25°C)
Input Overdrive = 1.0 V, Output to Ground
Source
Sink
VIO
DVIO/DT
IIB
IIO
AVOL
VOH
VOL
ISC
50
25
3.5
13.6
13.3
3.0
15
2.0
2.5
10
20
5.0
500
4.3
14.2
0.05
−14.2
5.0
27
4.5
5.0
6.5
100
200
20
40
0.15
−13.6
−13.3
mV
mV/°C
nA
nA
V/mV
V
mA
Input Common Mode Voltage Range
TA = +25°C
TA = Tlow to Thigh (Note 3)
VICR
VEE to (VCC −1.8)
VEE to (VCC −2.2)
Common Mode Rejection Ratio (RS 10 k), TA = +25°C
CMRR 80 90
Power Supply Rejection Ratio (RS = 100 W), TA = +25°C
PSRR
80 100
Power Supply Current (Per Amplifier)
VCC = +5.0 V, VEE = 0 V, TA = +25°C
VCC = +15 V, VEE = −15 V, TA = +25°C
VCC = +15 V, VEE = −15 V, TA = Tlow to Thigh (Note 3)
ID
− 180 250
− 220 250
− − 300
1. Either or both input voltages must not exceed the magnitude of VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded.
3. MC3317x
Tlow = −40°C
Thigh = +85°C
MC3317xV, NCV3317x
Tlow = −40°C
Thigh = +125°C
V
dB
dB
mA
www.onsemi.com
3


3Pages


MC33172 電子部品, 半導体
MC33171, 2, 4, NCV33172, 4
APPLICATIONS INFORMATION − CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the
MC33171/72/74 amplifier family is similar to low power op
amp products utilizing JFET input devices, these amplifiers
offer additional advantages as a result of the PNP transistor
differential inputs and an all NPN transistor output stage.
Because the input common mode voltage range of this
input stage includes the VEE potential, single supply
operation is feasible to as low as 3.0 V with the common
mode input voltage at ground potential.
The input stage also allows differential input voltages up
to ±44 V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
between VCC and VEE supply voltages as shown by the
maximum rating table. In practice, although not
recommended, the input voltages can exceed the VCC
voltage by approximately 3.0 V and decrease below the VEE
voltage by 0.3 V without causing product damage, although
output phase reversal may occur. It is also possible to source
up to 5.0 mA of current from VEE through either inputs’
clamping diode without damage or latching, but phase
reversal may again occur. If at least one input is within the
common mode input voltage range and the other input is
within the maximum input voltage range, no phase reversal
will occur. If both inputs exceed the upper common mode
input voltage limit, the output will be forced to its lowest
voltage state.
Since the input capacitance associated with the small
geometry input device is substantially lower (0.8 pF) than
that of a typical JFET (3.0 pF), the frequency response for
a given input source resistance is greatly enhanced. This
becomes evident in D−to−A current to voltage conversion
applications where the feedback resistance can form a pole
with the input capacitance of the op amp. This input pole
creates a 2nd Order system with the single pole op amp and
is therefore detrimental to its settling time. In this context,
lower input capacitance is desirable especially for higher
values of feedback resistances (lower current DACs). This
input pole can be compensated for by creating a feedback
zero with a capacitance across the feedback resistance, if
necessary, to reduce overshoot. For 10 kW of feedback
resistance, the MC33171/72/74 family can typically settle to
within 1/2 LSB of 8 bits in 4.2 ms, and within 1/2 LSB of 12
bits in 4.8 ms for a 10 V step. In a standard inverting unity
gain fast settling configuration, the symmetrical slew rate is
typically ± 2.1 V/ms. In the classic noninverting unity gain
configuration the typical output positive slew rate is also
2.1 V/ms, and the corresponding negative slew rate will
usually exceed the positive slew rate as a function of the fall
time of the input waveform.
The all NPN output stage, shown in its basic form on the
equivalent circuit schematic, offers unique advantages over
the more conventional NPN/PNP transistor Class AB output
stage. A 10 kW load resistance can typically swing within
0.8 V of the positive rail (VCC) and negative rail (VEE),
providing a 28.4 Vpp swing from ±15 V supplies. This large
output swing becomes most noticeable at lower supply
voltages.
The positive swing is limited by the saturation voltage of
the current source transistor Q7, the VBE of the NPN pull−up
transistor Q17, and the voltage drop associated with the
short circuit resistance, R5. For sink currents less than
0.4 mA, the negative swing is limited by the saturation
voltage of the pull−down transistor Q15, and the voltage
drop across R4 and R5. For small valued sink currents, the
above voltage drops are negligible, allowing the negative
swing voltage to approach within millivolts of VEE. For sink
currents (> 0.4 mA), diode D3 clamps the voltage across R4.
Thus the negative swing is limited by the saturation voltage
of Q15, plus the forward diode drop of D3 (VEE +1.0 V).
Therefore an unprecedented peak−to−peak output voltage
swing is possible for a given supply voltage as indicated by
the output swing specifications.
If the load resistance is referenced to VCC instead of
ground for single supply applications, the maximum
possible output swing can be achieved for a given supply
voltage. For light load currents, the load resistance will pull
the output to VCC during the positive swing and the output
will pull the load resistance near ground during the negative
swing. The load resistance value should be much less than
that of the feedback resistance to maximize pull−up
capability.
Because the PNP output emitter−follower transistor has
been eliminated, the MC33171/72/74 family offers a 15 mA
minimum current sink capability, typically to an output
voltage of (VEE +1.8 V). In single supply applications the
output can directly source or sink base current from a
common emitter NPN transistor for current switching
applications.
In addition, the all NPN transistor output stage is
inherently faster than PNP types, contributing to the bipolar
amplifier’s improved gain bandwidth product. The
associated high frequency low output impedance (200 W typ
@ 1.0 MHz) allows capacitive drive capability from 0 pF to
400 pF without oscillation in the noninverting unity gain
configuration. The 60° phase margin and 15 dB gain margin,
as well as the general gain and phase characteristics, are
virtually independent of the source/sink output swing
conditions. This allows easier system phase compensation,
since output swing will not be a phase consideration. The AC
characteristics of the MC33171/72/74 family also allow
excellent active filter capability, especially for low voltage
single supply applications.
Although the single supply specification is defined at
5.0 V, these amplifiers are functional to at least 3.0 V @
25°C. However slight changes in parametrics such as
bandwidth, slew rate, and DC gain may occur.
www.onsemi.com
6

6 Page



ページ 合計 : 15 ページ
 
PDF
ダウンロード
[ MC33172 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
MC33170

RF Amplifier Companion Chip for Dual-Band Cellular Subscriber Terminal

ON Semiconductor
ON Semiconductor
MC33171

(MC33172/MC33174) Low Power / Single Supply Operational Amplifiers

Motorola Semiconductors
Motorola Semiconductors
MC33171

(MC33171 - MC33174) Low Power Operational Amplifiers

ON Semiconductor
ON Semiconductor
MC33171

LOW POWER SINGLE BIPOLAR OPERATIONAL AMPLIFIERS

STMicroelectronics
STMicroelectronics


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap