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MC74VHC138のメーカーはON Semiconductorです、この部品の機能は「3-To-8 Line Decoder」です。 |
部品番号 | MC74VHC138 |
| |
部品説明 | 3-To-8 Line Decoder | ||
メーカ | ON Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとMC74VHC138ダウンロード(pdfファイル)リンクがあります。 Total 8 pages
MC74VHC138
3--to--8 Line Decoder
The MC74VHC138 is an advanced high speed CMOS 3--to--8
decoder fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 -- A2)
determine which one of the outputs (Y0 -- Y7) will go Low. When
enable input E3 is held Low or either E2 or E1 is held High, decoding
function is inhibited and all outputs go high. E3, E2, and E1 inputs are
provided to ease cascade connection and for use as an address decoder
for memory systems.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
• High Speed: tPD = 5.7ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 0.8 V (Max)
www.DataSheet4U.com
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates
• These devices are available in Pb--free package(s). Specifications herein
apply to both standard and Pb--free devices. Please see our website at
www.onsemi.com for specific Pb--free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
http://onsemi.com
MARKING DIAGRAMS
SOIC--16
D SUFFIX
CASE 751B
16 9
VHC138
AWLYYWW
18
16 9
TSSOP--16
DT SUFFIX
CASE 948F
VHC
138
AWLYWW
18
16 9
SOIC EIAJ--16
M SUFFIX
CASE 966
1
VHC138
ALYW
8
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC74VHC138D
SOIC--16 48 Units/Rail
MC74VHC138DR2 SOIC--16 2500 Units/Reel
MC74VHC138DT TSSOP--16 96 Units/Rail
MC74VHC138DTR2
MC74VHC138M
MC74VHC138MEL
TSSOP--16
SOIC
EIAJ--16
SOIC
EIAJ--16
2500 Units/Reel
48 Units/Rail
2000 Units/Reel
© Semiconductor Components Industries, LLC, 2006
March, 2006 -- Rev. 4
1
Publication Order Number:
MC74VHC138/D
1 Page MC74VHC138
EXPANDED LOGIC DIAGRAM
A0 1
A1 2
A2 3
E2 5
E1 4
E3 6
A0 1
A1 2
A2 3
E3 6
E2 5
E1 4
BIN/OCT
10
21
42
3
&4
5
EN 6
7
IEC LOGIC DIAGRAM
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
7 Y7
A0 1
A1 2
A2 3
E3 6
E2 5
E1 4
DMUX
0
G
0
7
2
0
1
2
3
&4
5
6
7
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
7 Y7
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
7 Y7
http://onsemi.com
3
3Pages A
tPLH
Y
VALID
50%
50% VCC
MC74VHC138
SWITCHING WAVEFORMS
VALID
tPHL
VCC
GND
E3
tPHL
Y
50%
50% VCC
Figure 2.
Figure 3.
VCC
GND
tPLH
E2 or E1 50%
Y
tPHL
50% VCC
Figure 4.
VCC
GND
tPLH
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 5. Test Circuit
INPUT
Figure 6. Input Equivalent Circuit
http://onsemi.com
6
6 Page | |||
ページ | 合計 : 8 ページ | ||
|
PDF ダウンロード | [ MC74VHC138 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
MC74VHC132 | Quad 2-Input NAND Schmitt Trigger | Motorola Semiconductors |
MC74VHC132 | Quad 2-Input NAND Schmitt Trigger | ON Semiconductor |
MC74VHC138 | 3-to-8 Line Decoder | Motorola Semiconductors |
MC74VHC138 | 3-To-8 Line Decoder | ON Semiconductor |