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PDF UC3843B Data sheet ( Hoja de datos )
| Número de pieza | UC3843B | |
| Descripción | (UC3842B / UC3843B) HIGH PERFORMANCE CURRENT MODE CONTROLLERS | |
| Fabricantes | ON Semiconductor | |
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UC3842B, UC3843B,
UC2842B, UC2843B
High Performance
Current Mode Controllers
The UC3842B, UC3843B series are high performance fixed
frequency current mode controllers. They are specifically designed for
Off−Line and DC−DC converter applications offering the designer a
cost−effective solution with minimal external components. These
integrated circuits feature a trimmed oscillator for precise duty cycle
control, a temperature compensated reference, high gain error
amplifier, current sensing comparator, and a high current totem pole
output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, programmable output deadtime, and a latch for single
pulse metering.
These devices are available in an 8−pin dual−in−line and surface
mount (SOIC−8) plastic package as well as the 14−pin plastic surface
mount (SOIC−14). The SOIC−14 package has separate power and
ground pins for the totem pole output stage.
The UCX842B has UVLO thresholds of 16 V (on) and 10 V (off),
ideally suited for off−line converters. The UCX843B is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
Features
• Trimmed Oscillator for Precise Frequency Control
• Oscillator Frequency Guaranteed at 250 kHz
• Current Mode Operation to 500 kHz
• Automatic Feed Forward Compensation
• Latching PWM for Cycle−By−Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output
• Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
• This is a Pb−Free and Halide−Free Device
VCC 7(12)
Vref
8(14)
R
5.0V
Reference
VCC
Undervoltage
Lockout
Vref
R Undervoltage
Lockout
VC
7(11)
RT/CT
Oscillator
Output
4(7)
Voltage
Feedback
+
Latching
PWM
6(10)
Power
Ground
Input -
5(8)
2(3)
Output
Compensation
1(1)
Error
Amplifier
GND 5(9)
Current
Sense
3(5) Input
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 1. Simplified Block Diagram
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8
1
14
1
8
1
PDIP−8
N SUFFIX
CASE 626
SOIC−14
D SUFFIX
CASE 751A
SOIC−8
D1 SUFFIX
CASE 751
PIN CONNECTIONS
Compensation 1
Voltage Feedback 2
Current Sense 3
RT/CT 4
8 Vref
7 VCC
6 Output
5 GND
(Top View)
Compensation 1
NC 2
Voltage Feedback 3
NC 4
Current Sense 5
NC 6
RT/CT 7
14 Vref
13 NC
12 VCC
11 VC
10 Output
9 GND
8 Power Ground
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 19 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
September, 2013 − Rev. 17
1
Publication Order Number:
UC3842B/D
1 page  
UC3842B, UC3843B, UC2842B, UC2843B
80
50
20
8.0
5.0
2.0 VCC = 15 V
TA = 25°C
0.8
10 k
20 k
50 k 100 k 200 k
500 k
fOSC, OSCILLATOR FREQUENCY (kHz)
1.0 M
Figure 2. Timing Resistor
versus Oscillator Frequency
100
1. CT = 10 nF
50 2. CT = 5.0 nF
3. CT = 2.0 nF
4. CT = 1.0 nF
20 5. CT = 500 pF
6. CT = 200 pF
10 7. CT = 100 pF
5.0
4
3
2
1
7
6
5
2.0
1.0
10 k
VCC = 15 V
TA = 25°C
20 k
50 k 100 k 200 k
500 k
fOSC, OSCILLATOR FREQUENCY (kHz)
1.0 M
Figure 3. Output Deadtime
versus Oscillator Frequency
9.0
VCC = 15 V
VOSC = 2.0 V
8.5
8.0
7.5
7.0
- 55
- 25 0
25 50 75 100
TA, AMBIENT TEMPERATURE (°C)
Figure 4. Oscillator Discharge Current
versus Temperature
125
100
90
80
70 Idischg = 8.54 mA
60
VCC = 15 V
CT = 3.3 nF
50 TA = 25°C
40
0.8 1.0
2.0 3.0 4.0 5.0 6.0 7.0 8.0
RT, TIMING RESISTOR (kW)
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor
2.55 V
2.50 V
VCC = 15 V
AV = -1.0
TA = 25°C
2.45 V
0.5 ms/DIV
Figure 6. Error Amp Small Signal
Transient Response
3.0 V
2.5 V
VCC = 15 V
AV = -1.0
TA = 25°C
2.0 V
1.0 ms/DIV
Figure 7. Error Amp Large Signal
Transient Response
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5
5 Page 
UC3842B, UC3843B, UC2842B, UC2843B
Undervoltage Lockout
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (VCC) and the reference output (Vref) are
each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 16 V/10 V for the UCX842B,
and 8.4 V/7.6 V for the UCX843B. The Vref comparator
upper and lower thresholds are 3.6 V/3.4 V. The large
hysteresis and low startup current of the UCX842B makes
it ideally suited in off−line converter applications where
efficient bootstrap startup techniques are required
(Figure 35). The UCX843B is intended for lower voltage
DC−to−DC converter applications. A 36 V Zener is
connected as a shunt regulator from VCC to ground. Its
purpose is to protect the IC from excessive voltage that can
occur during system startup. The minimum operating
voltage (VCC) for the UCX842B is 11 V and 8.2 V for the
UCX843B.
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull−down resistor.
The SOIC−14 surface mount package provides separate
pins for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the Ipk(max)
clamp level. The separate VC supply input allows the
designer added flexibility in tailoring the drive voltage
independent of VCC. A Zener clamp is typically connected
to this input when driving power MOSFETs in systems
where VCC is greater than 20 V. Figure 27 shows proper
power and control ground connections in a current−sensing
power MOSFET application.
Reference
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the
UC384XB. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short−
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse−width jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 mF) connected directly to VCC, VC,
and Vref may be required depending upon circuit layout.
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise−generating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulator’s closed loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 21A
shows the phenomenon graphically. At t0, switch
conduction begins, causing the inductor current to rise at a
slope of m1. This slope is a function of the input voltage
divided by the inductance. At t1, the Current Sense Input
reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at
a slope of m2, until the next oscillator cycle. The unstable
condition can be shown if a perturbation is added to the
control voltage, resulting in a small DI (dashed line). With
a fixed oscillator period, the current decay time is reduced,
and the minimum current at switch turn−on (t2) is increased
by DI + DI m2/m1. The minimum current at the next cycle
(t3) decreases to (DI + DI m2/m1) (m2/m1). This perturbation
is multiplied by m2/m1 on each succeeding cycle, alternately
increasing and decreasing the inductor current at switch
turn−on. Several oscillator cycles may be required before
the inductor current reaches zero causing the process to
commence again. If m2/m1 is greater than 1, the converter
will be unstable. Figure 21B shows that by adding an
artificial ramp that is synchronized with the PWM clock to
the control voltage, the DI perturbation will decrease to zero
on succeeding cycles. This compensating ramp (m3) must
have a slope equal to or slightly greater than m2/2 for
stability. With m2/2 slope compensation, the average
inductor current follows the control voltage, yielding true
current mode operation. The compensating ramp can be
derived from the oscillator and added to either the Voltage
Feedback or Current Sense inputs (Figure 34).
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11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet UC3843B.PDF ] | |
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