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PDF MC74LCX573 Data sheet ( Hoja de datos )
| Número de pieza | MC74LCX573 | |
| Descripción | Low-Voltage CMOS Octal Transparent Latch | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74LCX573
Low−Voltage CMOS
Octal Transparent Latch
Flow Through Pinout
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The MC74LCX573 is a high performance, non−inverting octal
transparent latch operating from a 2.3 to 3.6 V supply. High
impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX573 inputs to be safely driven from 5.0 V devices.
The MC74LCX573 contains 8 D−type latches with 3−state standard
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn
inputs enters the latches. In this condition, the latches are transparent,
i.e., a latch output will change state each time its D input changes.
When LE is LOW, the latches store the information that was present
on the D inputs a setup time preceding the HIGH−to−LOW transition
of LE. The 3−state standard outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard outputs are
enabled. When OE is HIGH, the standard outputs are in the high
impedance state, but this does not interfere with new data entering into
the latches. The LCX573 flow through design faciliwtawwte.DsataSehaeest4yU.cPomC
board layout.
Features
• Designed for 2.3 to 3.6 V VCC Operation
• 5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic
• Supports Live Insertion and Withdrawal
• IOFF Specification Guarantees High Impedance When VCC = 0 V
• LVTTL Compatible
• LVCMOS Compatible
• 24 mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (10 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500 mA
• ESD Performance: Human Body Model >2000 V
Machine Model >200 V
• Pb−Free Packages are Available*
http://onsemi.com
MARKING
DIAGRAMS
20
1
20
SOIC−20
DW SUFFIX
CASE 751D
1
LCX573
AWLYYWWG
20
1
20
TSSOP−20
DT SUFFIX
CASE 948E
1
LCX
573
ALYWG
G
20
1
20
SOEIAJ−20
M SUFFIX
CASE 967
1
74LCX573
AWLYWWG
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
May, 2005 − Rev. 7
1
Publication Order Number:
MC74LCX573/D
1 page  
MC74LCX573
DYNAMIC SWITCHING CHARACTERISTICS
Symbol
Characteristic
Condition
TA = +25°C
Min Typ Max
Unit
VOLP
Dynamic LOW Peak Voltage
(Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
0.8
0.6
V
V
VOLV
Dynamic LOW Valley Voltage
(Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
−0.8
−0.6
V
V
4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Condition
Typical
Unit
CIN Input Capacitance
CI/O Input/Output Capacitance
CPD Power Dissipation Capacitance
VCC = 3.3 V, VI = 0 V or VCC
VCC = 3.3 V, VI = 0 V or VCC
10 MHz, VCC = 3.3 V, VI = 0 V or VCC
7
8
25
pF
pF
pF
Dn Vmi
tPLH
On Vmo
Vmi
tPHL
Vmo
VCC
0V
VOH
VOL
WAVEFORM 1 − PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
OE
tPZH
On
Vmi
tPHZ
Vmo
Vmi
VCC
0V
VOH
VHZ
tPZL
tPLZ
On Vmo
VLZ
VOL
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Dn
LE 1.5 V
On
ts
tw
tPLH, tPHL
1.5 V
2.7 V
1.5 V
0V
th
2.7 V
1.5 V
0V
VOH
VOL
Symbol
Vmi
Vmo
3.3 V + 0.3 V
1.5 V
1.5 V
VHZ VOL + 0.3 V
VLZ VOL − 0.3 V
VCC
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOL − 0.3 V
2.5 V + 0.2 V
VCC/2
VCC/2
VOL + 0.15 V
VOL − 0.15 V
WAVEFORM 3 − LE to On PROPAGATION DELAYS, LE MINIMUM
PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns except when noted
Figure 3. AC Waveforms
http://onsemi.com
5
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC74LCX573.PDF ] | |
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