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PDF MC74LCX573 Data sheet ( Hoja de datos )
| Número de pieza | MC74LCX573 | |
| Descripción | LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC74LCX573 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage CMOS Octal
Transparent Latch
Flow Through Pinout
With 5V-Tolerant Inputs and Outputs
(3-State, Non-Inverting)
The MC74LCX573 is a high performance, non–inverting octal
transparent latch operating from a 2.7 to 3.6V supply. High impedance
TTL compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5V allows MC74LCX573 inputs to be
safely driven from 5V devices.
The MC74LCX573 contains 8 D–type latches with 3–state standard
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs
enters the latches. In this condition, the latches are transparent, i.e., a
latch output will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on the D inputs a
setup time preceding the HIGH–to–LOW transition of LE. The 3–state
standard outputs are controlled by the Output Enable (OE) input. When
OE is LOW, the standard outputs are enabled. When OE is HIGH, the
standard outputs are in the high impedance state, but this does not
interfere with new data entering into the latches. The LCX573 flow
through design facilitates easy PC board layout.
• Designed for 2.7 to 3.6V VCC Operation
www.DataSheet4U.com
• 5V Tolerant — Interface Capability With 5V TTL Logic
• Supports Live Insertion and Withdrawal
• IOFF Specification Guarantees High Impedance When VCC = 0V
• LVTTL Compatible
• LVCMOS Compatible
• 24mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (10µA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V; Machine Model >200V
MC74LCX573
LOW–VOLTAGE
CMOS OCTAL
TRANSPARENT LATCH
20
1
20
1
20
1
20
1
DW SUFFIX
PLASTIC SOIC
CASE 751D–04
M SUFFIX
PLASTIC SOIC EIAJ
CASE 967–01
SD SUFFIX
PLASTIC SSOP
CASE 940C–03
DT SUFFIX
PLASTIC TSSOP
CASE 948E–02
Pinout: 20–Lead (Top View)
VCC O0 O1 O2 O3 O4 O5 O6 O7 LE
20 19 18 17 16 15 14 13 12 11
PIN NAMES
Pins
Function
OE
LE
D0–D7
O0–O7
Output Enable Input
Latch Enable Input
Data Inputs
3–State Latch Outputs
1 2 3 4 5 6 7 8 9 10
OE D0 D1 D2 D3 D4 D5 D6 D7 GND
11/96
© Motorola, Inc. 1996
1
REV 3
1 page  
MC74LCX573
Dn 1.5V
tPLH
On
2.7V
1.5V
0V
tPHL
VOH
1.5V 1.5V
VOL
WAVEFORM 1 – PROPAGATION DELAYS
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
2.7V 2.7V
OE
tPZH
On
1.5V
tPHZ
1.5V
1.5V
tPZL
On
tPLZ
1.5V
Dn
0V
VCC
VOH – 0.3V LE
≈ 0V
≈ 3.0V
On
VOL + 0.3V
GND
1.5V
ts
tw
tPLH, tPHL
1.5V
1.5V
0V
th
2.7V
1.5V
0V
VOH
VOL
WAVEFORM 2 – OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
WAVEFORM 3 – LE to On PROPAGATION DELAYS, LE MINIMUM
PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES
tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted
Figure 1. AC Waveforms
PULSE
GENERATOR
VCC
DUT
RT
R1
CL RL
6V
OPEN
GND
LCX DATA
BR1339 — REV 3
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V
Open Collector/Drain tPLH and tPHL
6V
tPZH, tPHZ
GND
CL = 50pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 2. Test Circuit
5
MOTOROLA
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC74LCX573.PDF ] | |
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