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UR5596 の電気的特性と機能

UR5596のメーカーはUnisonic Technologiesです、この部品の機能は「MOS IC」です。


製品の詳細 ( Datasheet PDF )

部品番号 UR5596
部品説明 MOS IC
メーカ Unisonic Technologies
ロゴ Unisonic Technologies ロゴ 




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UR5596 Datasheet, UR5596 PDF,ピン配置, 機能
www.DataSheet4U.com
UNISONIC TECHNOLOGIES CO.,LTD
UR5596
DDR TERMINATION
REGULATOR
MOS IC
DESCRIPTION
The UTC UR5596 is a linear bus termination regulator and
designed to meet JEDEC SSTL-2(Stub-Series Terminated
Logic) specifications for termination of DDR-SDRAM. It also can
be used in SSTL-3 or HSTL(High-Speed Transceiver Logic)
scheme. The device contains a high-speed OP AMP to provide
excellent response to the load transients, and can deliver 1.5A
continuous current and transient peaks up to 3A in the
application as required for DDR-SDRAM termination.
The UTC UR5596 also incorporates a VSENSE pin to provide
superior load regulation and a VREF output as a reference for the
chipset and DIMMs. Besides, an active low shutdown (SHDN)
pin provides Suspend To RAM (STR) functionality. When SHDN
is pulled low the VTT output will tri-state providing a high
impedance output, but, VREF will remain active. A power savings
advantage can be obtained in this mode through lower
quiescent current.
Regarding the output, VTT is capable of sinking and sourcing
current while regulating the output voltage equal to VDDQ/2. The
output stage has been designed to maintain excellent load
regulation while preventing shoot through. The UTC UR5596
also incorporates two distinct power rails that separates the
analog circuitry from the power output stage. This allows a split
rail approach to be utilized to decrease internal power
dissipation and permits UTC UR5596 to provide a termination
solution for DDRII SDRAM.
FEATURES
* Source and sink current
* Low output voltage offset
* No external resistors required
* Linear topology
* Suspend To Ram (STR) functionality
* Low external component count
* Thermal shutdown protection
SOP-8
*Pb-free plating product number: UR5596L
ORDERING INFORMATION
Ordering Number
Normal
Lead Free Plating
UR5596-S08-R UR5596L-S08-R
UR5596-S08-T UR5596L-S08-T
Package
SOP-8
SOP-8
Packing
Tape Reel
Tube
www.unisonic.com.tw
Copyright © 2005 Unisonic Technologies Co.,LTD
1
QW-R502-045,A

1 Page





UR5596 pdf, ピン配列
UR5596
MOS IC
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
Junction Temperature
Operation Temperature(Note 2)
Storage Temperature
Thermal Resistance Junction-Ambient
PVIN, AVIN, VDDQ to GND
AVIN to GND(Note 1)
VDD
VDD
TJ
TOPR
TSTG
θJA
-0.3 ~ +6
2.2 ~ 5.5
125
-20 ~ +85
-40 ~ +150
150
V
V
/W
Note: 1.Signified recommend operating range that indicates conditions for which the device is intended to be
functional, but does not guarantee specific performance limits.
2.The device is guaranteed to meet performance specification within 0~70operating temperature range
and assured by design from –20~+85.
3.Absolute maximum ratings indicate limits beyond which damage to the device may occur.
ELECTRICAL CHARACTERISTICS
(TJ=25°C, VIN=AVIN=PVIN=2.5V, VDDQ=2.5V, unless otherwise specified).
PARAMETER
SYMBOL TEST CONDITIONS
VREF Voltage
VTT Output Voltage
IOUT = 0A
IOUT = ±1.5A
Minimum Shutdown Level
High
Low
VTT Output Voltage Offset (VREF - VTT)
VREF
VTT
VIH
VIL
VosTT
VTT
VIN = VDDQ = 2.3V
VIN = VDDQ = 2.5V
VIN = VDDQ = 2.7V
VIN = VDDQ = 2.3V
VIN = VDDQ = 2.5V
VIN = VDDQ = 2.7V
VIN = VDDQ = 2.3V
VIN = VDDQ = 2.5V
VIN = VDDQ = 2.7V
IOUT = 0A
IOUT = -1.5A
IOUT = +1.5A
Quiescent Current
Quiescent Current in Shutdown
IQ IOUT = 0A
ISD SD = 0V
Shutdown Leakage Current
VTT Leakage Current in Shutdown
IQ_SD
IV
SD = 0V
SD = 0V
VTT = 1.25V
VSENSE Input Current
VREF Output Impedance
ISENSE
ZVREF
IREF = -30 ~ +30 µA
VDDQ Input Impedance
Thermal Shutdown
ZVDDQ
TSD
Thermal Shutdown Hysteresis
TSD-HYS
MIN
1.135
1.235
1.335
1.125
1.225
1.325
1.125
1.225
1.325
1.9
-20
-25
-25
TYP
1.158
1.258
1.358
1.159
1.259
1.359
1.159
1.259
1.359
0
0
0
320
115
2
1
13
2.5
100
165
10
MAX
1.185
1.285
1.385
1.190
1.290
1.390
1.190
1.290
1.390
0.8
20
25
25
500
150
5
10
UNIT
V
V
V
mV
µA
µA
µA
µA
nA
k
k
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
3
QW-R502-045,A


3Pages


UR5596 電子部品, 半導体
UR5596
MOS IC
TYPICAL APPLICATION CIRCUITS
Following demonstrate several different application circuits to illustrate some of the options that are possible in
configuring the UTC UR5596. The individual circuit performance can be found in the Typical Performance
Characteristics that curve graphs illustrate how the maximum output current is affected by changes in AVIN and PVIN.
STUB-SERIES TERMINATED LOGIC(SSTL) TERMINATION SCHEME
SSTL was created to improve signal integrity of the data transmission across the memory bus. This termination
scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered
with DDR-SDRAM. Class II single parallel termination(SSTL-2) is the most popular termination form. It involves one
RS series resistor from the chipset to the memory and one RT termination resistor (refer to Figure 1). RS and RT are
changeable to meet the current requirement from UR5596, the recommended values both RS and RT are 25Ω.
VDD
VTT
CHIPSET
RS RT MEMORY
VREF
Figure 1. SSTL-Termination Scheme
FOR SSTL-2 APPLICATIONS
For the majority of applications that implement the SSTL- 2 termination scheme, it is recommended to connect all
the input rails to the 2.5V rail as Figure 2. This provides an optimal trade-off between power dissipation and
component count and selection.
UTC UR5596
SHDN
VDDQ=2.5V
VDD=2.5V
SHDN
VDDQ
AVIN
VREF
VSENSE
+
CREF
VREF=1.25V
CIN +
PVIN
GND
VTT
+
COUT
VTT=1.25V
Figure 2. Recommended SSTL-2 Implementation
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
6
QW-R502-045,A

6 Page



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共有リンク

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部品番号部品説明メーカ
UR5595

DDR TERMINATION REGULATOR

Unisonic Technologies
Unisonic Technologies
UR5596

MOS IC

Unisonic Technologies
Unisonic Technologies


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