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Número de pieza | IRS21303 | |
Descripción | (IRS2130 - IRS2132) 3-PHASE BRIDGE DRIVER | |
Fabricantes | International Rectifier | |
Logotipo | ||
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PRELIMINARY
Data Sheet No. PD60274 revA
IRS2130/IRS21303/IRS2132 (J&S)PbF
3-PHASE BRIDGE DRIVER
Features
• Floating channel designed for bootstrap operation
• Fully operational to +600 V
• Tolerant to negative transient voltage, dV/dt immune
• Gate drive supply range from 10 V to 20 V
• Undervoltage lockout for all channels
• Over-current shutdown turns off all six drivers
• Three Independent half-bridge drivers
• Matched propagation delay for all channels
• 2.5 V logic compatible
• Outputs out of phase with inputs
• Cross-conduction prevention logic
• All parts are LEAD-FREE
Product Summary
VOFFSET
600 V max.
IO+/- (min.)
200 mA / 420 mA
VOUT
ton/off (typ.)
10 V – 20 V (IRS213(0,2))
13 V – 20 V (IRS21303)
500 ns
Deadtime (typ.)
2.0 µs (IRS2130)
0.7 µs (IRS213(2,03))
Applications:
*Motor Control
*Air Conditioners/ Washing Machines
*General Purpose Inverters
*Micro/Mini Inverter Drives
Description
Packages
The IRS213(0, 03, 2) are high voltage, high speed
power MOSFET and IGBT drivers with three independent
high and low side referenced output channels. Proprietary
HVIC technology enables ruggedized monolithic
construction. Logic inputs are compatible with CMOS or
LSTTL outputs, down to 2.5 V logic. A ground-referenced
operational amplifier provides analog feedback of bridge
current via an external current sense resistor. A current trip
28-Lead SOIC
28-Lead PDIP
function which terminates all six outputs is also derived from
this resistor. An open drain FAULT signal indicates if an
over-current or undervoltage shutdown has occurred. The
output drivers feature a high pulse current buffer stage
designed for minimum driver cross-conduction. Propagation
delays are matched to simplify use at high frequencies. The
floating channels can be used to drive N-channel power
44-Lead PLCC w/o 12 Leads
MOSFETs or IGBTs in the high side configuration which operates up to 600 V.
Typical Connection
www.irf.com
1
1 page IRS2130/IRS21303/IRS2132 (J&S)PbF
Static Electrical Characteristics - (Continued)
PRELIMINARY
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH, and IIN parameters
are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are
referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
Symbol
ISRC,AMP
ISNK,AMP
IO+,AMP
IO-,AMP
Definition
Operational amplifier output source current
Operational amplifier output sink current
Operational amplifier output high short circuit
current
Operational amplifier output low short circuit
current
Min. Typ. Max. Units Test Conditions
4 7—
1 2.1 —
— 10 —
—4—
VCA- = 0 V, VSO =1 V
VCAO = 4 V
VCA- = 1 V, VSO =0 V
mA
VCAO = 2 V
VCA- = 0 V, VSO =5 V
VCAO = 0 V
VCA- = 5 V, VSO =0 V
VCAO = 5 V
Dynamic Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified.
Symbol
ton
toff
tr
tf
titrip
tbl
tflt
tflt, in
tfltclr
DT
SR+
SR-
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
ITRIP to output shutdown propagation delay
ITRIP blanking time
ITRIP to FAULT indication delay
Input filter time (all six inputs)
LIN1,2,3 to FAULT clear time IRS213(0,2)
LIN1,2,3 & HIN1,2,3 to FAULT clear time
IRS21303
Deadtime
IRS2130
IRS213(2,03)
Operational amplifier slew rate (+)
Operational amplifier slew rate (-)
Min. Typ. Max. Units Test Conditions
400 500 700
400 500 700
— 80 125
— 35 55
400 660 920
— 400 —
350 550 870
— 325 —
VS1,2,3 = 0 V to 600 V
ns
5300 8500 13700
1300 2000 3100
500 700 1100
5 10 —
2.4 3.2 —
V/µs
1 V input step
NOTE: For high side PWM, HIN pulse width must be > 1.5 µs.
www.irf.com
5
5 Page IRS2130/IRS21303/IRS2132 (J&S)PbF
PRELIMINARY
1 PCB Layout Tips
1.1 Distance from H to L Voltage
The IRS213(0,03,2)J package lacks some pins (see page 8) in order to maximizing the distance between the high
voltage and low voltage pins. It’s strongly recommended to place the components tied to the floating voltage in the
respective high voltage portions of the device (VB1,2,3, VS1,2,3) side.
1.2 Ground Plane
To minimize noise coupling the ground plane must not be placed under or near the high voltage floating side.
1.3 Gate Drive Loops
Current loops behave like an antenna able to receive and transmit EM noise (see Fig. 7). In order to reduce EM
coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as
possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic
capacitance. The parasitic auto-inductance of the gate loop contributes to develop a voltage across the gate-emitter
increasing the possibility of self turn-on effect.
VBX (VCC)
HOX ( LOX )
gate
resistance
IGC
CGC
VSX ( Vs0 )
Gate Drive
Loop
VGE
Fig. 7. Antenna Loops
1.4 Supply Capacitors
Supply capacitors must be placed as close as possible to the device pins (VCC and VSS for the ground tied supply, VB
and VS for the floating supply) in order to minimize parasitic inductance/resistance.
1.5 Routing and Placement
Power stage PCB parasitic may generate dangerous voltage transients for the gate driver and the control logic. In
particular it’s recommended to limit phase voltage negative transients.
In order to avoid such undervoltage it is highly recommended to minimize high side emitter to low side collector
distance and low side emitter to negative bus rail stray inductance. See DT04-4 at www.irf.com for more detailed
information.
www.irf.com
11
11 Page |
Páginas | Total 22 Páginas | |
PDF Descargar | [ Datasheet IRS21303.PDF ] |
Número de pieza | Descripción | Fabricantes |
IRS2130 | (IRS2130 - IRS2132) 3-PHASE BRIDGE DRIVER | International Rectifier |
IRS21303 | (IRS2130 - IRS2132) 3-PHASE BRIDGE DRIVER | International Rectifier |
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