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FIN324C の電気的特性と機能

FIN324CのメーカーはFairchild Semiconductorです、この部品の機能は「24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays」です。


製品の詳細 ( Datasheet PDF )

部品番号 FIN324C
部品説明 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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FIN324C Datasheet, FIN324C PDF,ピン配置, 機能
www.DataSheet4U.com
March 2007
FIN324C
24-Bit Ultra-Low Power Serializer Deserializer
Supporting Single and Dual Displays
Features
ƒ Ultra-Low Operating Power: ~4mA at 5.44MHz
ƒ Supports Dual-Display Implementations with RGB
or Microcontroller Interface
ƒ No External Timing Reference Needed
ƒ SPI Mode Support
ƒ Single Device Operates as a Serializer or
Deserializer
ƒ Direct Support for Motorola®-Style R/W
Microcontroller Interface
ƒ Direct Support for Intel®-Style /WE, /RE
Microcontroller Interface
ƒ 15MHz Maximum Strobe Frequency
ƒ Utilizes Fairchild’s Proprietary CTL Serial I/O
Technology
ƒ Available in BGA and MLP packages
ƒ Wide Parallel Supply Voltage Range: 1.60 to 3.0V
ƒ Low Power Core Operation: VDDS/A=2.5 to 3.0V
ƒ Voltage Translation Capability Across Pair with No
External Components
ƒ High ESD protection: >14.5kV HBM
ƒ Power-Saving Burst-Mode Operation
Applications
ƒ Single or Dual 16/18-Bit RGB Cell Phone Displays
ƒ Single or Dual 16/18-Bit Cell Phone Displays with
Microcontroller Interface
ƒ Single or Dual Mobile Display at QVGA or HVGA
Resolution
Description
The FIN324C is a 24-bit serializer / deserializer with dual
strobe inputs. The device can be configured as a master
or slave device through the master/slave select pin
(M/S). This allows for the same device to be used as
either a serializer or deserializer, minimizing component
types in the system. The dual strobe inputs allow
implementation of dual-display systems with a single
pair of µSerDes. The FIN324C can accommodate RGB,
microcontroller, or SPI mode interfaces. Read and write
transactions are supported when operating with a
Motorola-style microcontroller interface for one or both
displays. Unlike other SerDes solutions, no external
timing reference is required for operation.
The FIN324C is designed for ultra-low power operation.
Reset (/RES) and standby (/STBY) signals put the
device in an ultra-low power state. In standby mode, the
outputs of the slave device maintain state, allowing the
system to resume operation from the last-known state.
The device utilizes Fairchild’s proprietary ultra-low power,
low-EMI Current Transfer Logic™ (CTL) technology. The
serial interface disables between transactions to minimize
EMI at the fundamental serial interface and to conserve
power. LV-CMOS parallel output buffers have been
implemented with slew rate control to adjust for capacitive
loading and to minimize EMI.
The serialization bit clock is generated internally to the
FIN324C. The minimum bit clock frequency is always
great enough to handle the maximum strobe frequency.
Related Application Notes
ƒ AN-5058 µSerDes™ Family Frequently Asked
Questions
ƒ AN-5061 µSerDes™ Layout Guidelines
ƒ AN-6047 FIN324C Reset and Standby
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
www.fairchildsemi.com

1 Page





FIN324C pdf, ピン配列
Pin Definitions
Pin
I/O #
Type Pins
Description of Signals
Chip-Level Control Signals
M/S IN
1
/RES
IN 1
/STBY(SLEW)
IN
1
PAR/SPI
IN 1
CKSEL(H)
IN 1
LV-CMOS Master/Slave Control Input:
M/S=1 MASTER, M/S =0 SLAVE
LV_CMOS RESET signal and power-down signal
/RES=0: Resets and powers down all circuitry
/RES=1: Device enabled
LV-CMOS standby signal or output slew rate signal:
M/S=1: /STBY
M/S=0: RSLEW
/STBY=0: Device powered down
RSLEW=1: Fast edge rate
RSLEW=0: Slow edge rate
LV-CMOS parallel / SPI display interface
Tells the SerDes it is interfacing with a sub-display with a SPI interface
PAR/SPI=1: Parallel Interface
PAR/SPI=0: SPI Interface using STRB0(WCLK0)
LV-CMOS Input: Master clock source select input.
When M/S=1: CKSEL (passed in serial stream)
CKSEL=1: STRB1(WCLK1) Active
CKSEL=0: STRB0(WCLK0) Active
When M/S=0: This pin must be tied to VDDP.
Parallel Interface Signals Master Functionality (Slave Functionality)
DP[17:0]
DP[6]({SCLK})
DP[7]({SDAT})
I/O
LV-CMOS data I/O. I/O direction controlled by M/S pin and R/W
18
internal state.
DP[6] SPI mode SCLK signal pin when PAR/SPI=0 (Slave Only)
DP[7] SPI mode SDAT signal pin when PAR/SPI=0(Slave Only)
CNTL[5:0]
{SCLK}CNTL[5]
{SDAT}CNTL[4]
I/O
LV-CMOS data I/O. I/O direction controlled by M/S pin
6
M/S=1: Inputs
M/S=0: Outputs
In SPI mode, CNTL[5] is SCLK; CNTL[4] is SDAT for master and slave
LV-CMOS data I/O. I/O direction controlled by M/S pin.
M/S=1: Input
R/W
I/O
1
M/S=0: Output
Functional operation:
R/W=1: Read
R/W=0: Write
STRB0(WCLK0)
I/O
LV-CMOS data I/O. Function controlled by M/S pin.
1 M/S=1: STRB0 Input
M/S=0: WCLK0 Output
STRB1(WCLK1)
I/O
LV-CMOS Data I/O. Function controlled by M/S pin.
1 M/S=1: STRB1 Input
M/S=0: WCLK1 Output
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
3
www.fairchildsemi.com


3Pages


FIN324C 電子部品, 半導体
System Control Pins
(M/S) Master / Slave Selection: A given device can be
configured as a master or slave device based on the
state of the M/S pin.
Table 1. Master/Slave
M/S
0
1
Configuration
Slave Mode
Master Mode
(PAR/SPI) SPI Mode Selection: The PAR/SPI signal
configures STRB0(WCLK0) for SPI mode write operation.
STRB1(WCLK1) always operates in parallel mode.
Control signals CNTL[5:0] all pass in SPI mode. In SPI
mode, the SCLK signal is used to strobe the serializer.
SPI mode supports SPI writes only.
Table 2. Channel 0 PAR/SPI Configuration
PAR
/SPI
M/S=1 MASTER
M/S=0 SLAVE
SDAT=CNTL[4] SDAT=DP[7] & CNTL[4]
0 SCLK=CNTL[5] SCLK=DP[6] & CNTL[5]
/CS=STRB0
/CS=WCLK0
1 Parallel Mode
Parallel Mode
(CKSEL) Strobe Selection Signal: The CKSEL signal
exists only on the master device and determines which
strobe signal is active. The active strobe signal is
selected by CKSEL and PAR/SPI inputs.
Table 3. PAR/SPI
PAR CKSEL
/SPI
00
01
10
11
Master
Strobe
Source
CNTL[5]
STRB1
STRB0
STRB1
Slave Strobe
Source
DP[6] & CNTL[5]
WCLK1
WCLK0
WCLK1
(/RES, /STBY) Reset and Standby Mode Functionality:
Reset and standby mode functionality is determined by
the state of the /RES and /STBY signals for the master
device and the /RES and internal standby-detect signal for
the slave device. The /RES control signal has a filter that
rejects spurious pulses on /RES.
Table 4. Reset and Standby Modes
/RES /STBY(3)
Master
0 X Reset Mode
1 0 Standby Mode
1 1 Operating Mode
Slave
Reset Mode
Standby
Mode(3)
Operating
Mode
Note:
3. The slave device is put into standby mode through
control signals sent from the master device.
Table 5. Reset and Standby Mode States
Pin
Master
Slave
Reset / Standby Reset
DP[17:0]
CNTL[5:0]
STRB[0:1]
(WCLK[0:1])
Disabled
Disabled
Disabled
Low
Low
High
Slave
Standby
Last data
Last data
High
(SLEW) Slew Control: The slew control operates only
when in slave mode. This signal changes the edge rate
of the DP[17:0], CNTL[5:0], R/W, WCLK1, and WCLK0
signals to optimize edge rate for the load being driven.
Master read mode outputs have “slow” edge rates.
Table 6. Slew Rate Control
/STBY (SLEW)
0
1
Slave M/S=0
“Slow”
“Fast”
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
6
www.fairchildsemi.com

6 Page



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部品番号部品説明メーカ
FIN324C

24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays

Fairchild Semiconductor
Fairchild Semiconductor


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