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PDF 74FST6800 Data sheet ( 特性 )

部品番号 74FST6800
部品説明 10-Bit Bus Switch
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 

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74FST6800 Datasheet, 74FST6800 PDF,ピン配置, 機能
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74FST6800
10−Bit Bus Switch with
Precharged Outputs
The ON Semiconductor 74FST6800 is a 10bit bus switch with
precharged outputs. The device is CMOS TTL compatible when
operating between 4.0 and 5.5 Volts. The device exhibits extremely
low RON and adds nearly zero propagation delay. The device adds no
noise or ground bounce to the system.
Features
RON t 4 W Typical
Less Than 0.25 nsMax Delay Through Switch
Nearly Zero Standby Current
No Circuit Bounce
Control Inputs are TTL/CMOS Compatible
PinForPin Compatible With QS6800, FST6800, CBT6800
All Popular Packages: SOIC24, TSSOP24, QSOP24
All Devices in Package TSSOP are Inherently PbFree*
OE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
GND
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
VCC
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BIASV
Figure 1. 24Lead Pinout
http://onsemi.com
24
1
SOIC24
DW SUFFIX
CASE 751E
MARKING
DIAGRAMS
24
FST6800
AWLYWW
1
24
1
TSSOP24
DT SUFFIX
CASE 948H
24
FST
6800
ALYW
1
24
1
QSOP24
QS SUFFIX
CASE 492B
24
FST6800
AWLYYWW
1
TRUTH TABLE
OE B0B9 Function
L A0A9 Connect
H
Bias V
Precharge
NOTE:
H = HIGH Voltage Level
L = LOW Voltage Level
A
L, WL
Y, YY
W, WW
=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
PIN NAMES
Pin
OE
A
B
Description
Bus Switch Enable
Bus A
Bus B
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 Rev. 6
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
74FST6800/D

1 Page





74FST6800 pdf, ピン配列
74FST6800
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Max
VCC
VI
VO
TA
Dt/DV
Supply Voltage
Input Voltage
Output Voltage
Operating FreeAir Temperature
Input Transition Rise or Fall Rate
Switch I/O
Operating, Data Retention Only
(Note 5)
(HIGH or LOW State)
Switch Control Input
VCC = 5.0 V $ 0.5 V
4.0
0
0
*40
0
5.5
5.5
5.5
)85
DC
5
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
Unit
V
V
V
°C
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
VCC TA = *405C to )855C
(V) Min Typ* Max Unit
VIK Clamp Diode Resistance
IIN = *18mA
4.5 *1.2 V
VIH HighLevel Input Voltage
4.0 to 5.5 2.0
V
VIL LowLevel Input Voltage
4.0 to 5.5
0.8 V
II Input Leakage Current
0 v VIN v 5.5 V
IOZ OFFSTATE Leakage Current 0 v A, B v VCC
5.5 $1.0 mA
5.5 $1.0 mA
RON Switch On Resistance (Note 6) VIN = 0 V, IIN = 64 mA
4.5 4 7 W
VIN = 0 V, IIN = 30 mA
4.5 4 7
VIN = 2.4 V, IIN = 15 mA
4.5 8 15
VIN = 2.4 V, IIN = 15 mA
4.0 11 20
ICC Quiescent Supply Current
VIN = VCC or GND, IOUT = 0
5.5
3 mA
DICC Increase In ICC per Input
One input at 3.4 V, Other inputs at VCC or GND
5.5
2.5 mA
*Typical values are at VCC = 5.0 V and TA = 25°C.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltages on the two (A or B) pins.
AC ELECTRICAL CHARACTERISTICS
TA = *405C to )855C
CL = 50 pF, RU = RD = 500 W
VCC = 4.55.5 V
VCC = 4.0 V
Symbol
Parameter
Conditions
Min Max Min Max Unit
tPHL,
tPLH
Prop Delay Bus to Bus (Note 7)
VI = OPEN
0.25 0.25 ns
tPZH,
tPZL
Output Enable Time, IOE to Bus A, B
Bias V = GND
VI = OPEN for tPZH
1.0 5.1
5.6 ns
tPHZ,
tPLZ
Output Disable Time, IOE to Bus A, B
Bias V = GND
VI = OPEN for tPHZ
1.0 5.5
5.5 ns
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol
Parameter
Conditions
CIN Control Pin Input Capacitance
VCC = 5.0 V
CI/O A/B Port Input/Output Capacitance
VCC, OE = 5.0 V
8. TA = )25°C, f = 1 MHz, Capacitance is characterized but not tested.
Typ Max Unit
3 pF
5 pF
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3


3Pages


74FST6800 電子部品, 半導体
A
B
LP
0.25 (0.010) M T
74FST6800
PACKAGE DIMENSIONS
QSOP24
QS SUFFIX
CASE 492B01
ISSUE O
R
U
G
Q
H x 45_
RAD.
0.013 X 0.005
DP. MAX
RAD.
0.0050.010
TYP
DETAIL E
MOLD PIN
MARK
K
C 24 PL D
T
SEATING
PLANE
0.25 (0.010) M T B S A S
V
J
M
N 8 PL
F
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN
THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE
ONLY). BOTTOM PACKAGE DIMENSION SHALL
FOLLOW THE DIMENSION STATED IN THIS
DRAWING.
4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 6 MILS PER
SIDE.
5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.
INCHES
DIM MAX MIN
A 0.337 0.344
B 0.150 0.157
C 0.061 0.068
D 0.008 0.012
F 0.016 0.035
G 0.025 BSC
H 0.008 0.018
J 0.0098 0.0075
K 0.004 0.010
L 0.230 0.244
M 0_ 8_
N 0_ 7_
P 0.027 0.037
Q 0.035 DIA
R 0.035 0.045
U 0.035 0.045
V 0_ 8_
MILLIMETERS
MAX MIN
8.56 8.74
3.81 3.99
1.55 1.73
0.20 0.31
0.41 0.89
0.64 BSC
0.20 0.46
0.249 0.191
0.10 0.25
5.84 6.20
0_ 8_
0_ 7_
0.69 0.94
0.89 DIA
0.89 1.14
0.89 1.14
0_ 8_
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 8002829855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81357733850
http://onsemi.com
6
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
74FST6800/D

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