PDF IS61LV2568 Data sheet ( Hoja de datos )

Número de pieza	IS61LV2568
Descripción	256K x 8 HIGH-SPEED CMOS STATIC RAM
Fabricantes	ISSI
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No Preview Available ! www.DataSheet4U.com IS61LV2568 256K x 8 HIGH-SPEED CMOS STATIC RAM ISSI® FEBRUARY 2003 FEATURES • High-speed access times: 10 and 12 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Low power: 540 mW @ 10 ns 36 mW standby mode • TTL compatible inputs and outputs • Single 3.3V ±10% power supply • Packages available: – 36-pin 400-mil SOJ – 44-pin TSOP (Type II) DESCRIPTION The ISSI IS61LV2568 is a very high-speed, low power, 262,144-word by 8-bit CMOS static RAM. The IS61LV2568 is fabricated using ISSI's high-performance CMOS tech- nology. This highly reliable process coupled with innova- tive circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 36mW (max.) with CMOS input levels. The IS61LV2568 operates from a single 3.3V power supply and all inputs are TTL-compatible. The IS61LV2568 is available in 36-pin 400-mil SOJ, and 44-pin TSOP (Type II) packages. FUNCTIONAL BLOCK DIAGRAM A0-A17 VDD GND I/O0-I/O7 DECODER 256K X 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O CE CONTROL OE CIRCUIT WE Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 02/07/03 1 1 page IS61LV2568 AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 ISSI ® AC TEST LOADS 319 Ω 3.3V OUTPUT 30 pF Including jig and scope 353 Ω Figure 1 319 Ω 3.3V OUTPUT 5 pF Including jig and scope 353 Ω Figure 2 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter tRC Read Cycle Time tAA Address Access Time tOHA Output Hold Time tACE CE Access Time tDOE OE Access Time tLZOE(2) OE to Low-Z Output tHZOE(2) OE to High-Z Output tLZCE(2) CE to Low-Z Output tHZCE(2) CE to High-Z Output -10 ns Min. Max. 10 — — 10 3— — 10 —4 0— 04 3— 04 -12 ns Min. Max. 12 — — 12 3— — 12 —5 0— 05 3— 05 Unit ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 02/07/03 5 5 Page

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