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PDF IS34C02B Data sheet ( Hoja de datos )
| Número de pieza | IS34C02B | |
| Descripción | 2K-bit 2-WIRE SERIAL CMOS EEPROM | |
| Fabricantes | ISSI | |
| Logotipo |  |
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IS34C02B
ISSI®
2K-bit 2-WIRE SERIAL CMOS EEPROM
with Permanent and Reversible Write-Protection
ADVANCED INFORMATION
APRIL 2006
FEATURES
• Two-Wire Serial Interface, I2CTM compatible
– Bidirectional data transfer protocol
– 400 kHz (2.5V) and 100 KHz (1.7V) compat-
ibility
• Organization:
– 256 x 8-bit
• Data Protection Features
– Write Protect Pin
– Permanent Software Protection
– Reversible Software Protection
• 16-Byte Page Write Buffer
– Partial Page-writes permitted
• Low Power CMOS Technology
– Active Current less than 3 mA (3.6V)
– Standby Current less than 1 µA (1.7V)
– Standby Current less than 2 µA (3.6V)
• Low Voltage Operation
– IS34C02B-2: Vcc = 1.7V to 3.6V
• Random or Sequential Read Modes
• Filtered Inputs for Noise Suppression
• Self timed Write cycle (5ms max.)
• High Reliability
– Endurance: 1,000,000 Cycles
– Data Retention: 40 Years
• Industrial temperature range
• 8-pin TSSOP and DFN (leadless array)
• Lead-free available
DESCRIPTION
The IS34C02B is an electrically erasable PROM device
that uses the industry-standard I2C communication
protocol. The IS34C02B contains a non-volatile memory
array of 2,048-bits (256K x 8 bytes), and is further
subdivided into 16 pages of 16 bytes each for Page-
write mode. The device operates over the voltage range
of 1.7V to 3.6V to satisfy the voltage requirements of
DDR2, DDR1, and many other specifications. In normal
Read or Write operations, a master device communi-
cates with the EEPROM via the two wires Serial Clock
and Serial Data. During application system boot-up, it
may be necessary to read out the contents of the
IS34C02B that pertain to the configuration of a DRAM
module. If the module manufacturer wishes to safe-
guard this memory content, the first half of the array can
be write-protected with either a permanent or reversible
software command, or the entire array can be write-
protected with the WP input pin. The IS34C02B hashttp://www.DataSheet4U.net/
three address pins, allowing up to eight devices (or
memory modules) to be uniquely accessible in a sys-
tem. To minimize board real-estate, IS34C02B is
available in two space-saving packages: TSSOP(8), and
DFN(8). All these features make the device ideal for
use as a Serial Presence Detect (SPD) EEPROM in
various types of memory modules.
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published
information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev.00D
03/21/06
1
datasheet pdf - http://www.DataSheet4U.net/
1 page  
IS34C02B
ISSI ®
WRITE OPERATION
WRITE PROTECTION
Byte Write
Hardware Write Protection
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends a byte address that is written into
theaddresspointeroftheIS34C02B. Afterreceivinganother
ACK from the Slave, the Master device transmits the data
byte to be written into the address memory location. The
IS34C02B acknowledges once more and the Master
generates the Stop condition, at which time the device
begins its internal programming cycle. While this internal
cycle is in progress, the device will not respond to any
request from the Master device.
Page Write
The IS34C02B has two forms of software write protec-
tion and one form of hardware write protection. The
hardware write protection is enabled when the WP input
is held High. In this case, the entire array of the
IS34C02B is read-only regardless of the status of the
software protection. The hardware protection is disabled
when the WP input is held Low or is floating. In this
case, the upper half of the array (80h-FFh) can be
modified by a valid Write command, and the lower half of
the array (00h-7Fh) can be modified only if software write
protection has not been enabled.
Reversible Software Write Protection
The IS34C02B is capable of 16-byte Page-Write operation.
A Page-Write is initiated in the same manner as a Byte Write,
but instead of terminating the internal Write cycle after the
first data byte is transferred, the Master device can transmit
up to 15 more bytes. After the receipt of each data byte, the
IS34C02B responds immediately with an ACK on SDA line,
and the four lower order data byte address bits are internally
incremented by one, while the higher order bits of the data
byte address remain constant. If a byte address is
incremented from the last byte of a page, it returns to the first
byte of that page. If the Master device should transmit more
than 16 bytes prior to issuing the Stop condition, the address
counter will “roll over,” and the previously written data will be
overwritten. Once all 16 bytes are received and the Stop
condition has been sent by the Master, the internal
programming cycle begins. At this point, all received data is
written to the IS34C02B in a single Write cycle. All inputs are
disabled until completion of the internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
IS34C02B initiates the internal Write cycle. ACK polling can
be initiated immediately. This involves issuing the Start
condition followed by the Slave address for a Write operation.
If the IS34C02B is still busy with the Write operation, no
No Acknowledge (NoACK) will be returned. If the IS34C02B
has completed the Write operation, an ACK will be returned
and the host can then proceed with the next Read or Write
operation.
There is a non-volatile flag for each of the two forms of
software write protection. When the bit value for either
flag or both flags is 1, it is not possible to modify the
contents of the lower 128 bytes of the array (00h-7Fh). If
the bit value for both flags is 0, it is possible to modify
this half of the array with a valid Write command,
assuming WP is held Low or is floating. The device is
shipped with both flags cleared. One of those flags is
http://www.DataSheet4U.net/
the Reversible Software Write Protection (RSWP) flag,
and can be changed with the Set RSWP and Clear
RSWP commands. The flag can also be verified without
being changed with a Read SWP command. In order to
set, clear or read the RSWP, the IS34C02B input pins
must be as follows: A0 must be held to an extra high
voltage of VHV (see DC Characteristics), while A2 and
A1 must be set High, Low, or left floating, depending on
the desired command (see Figure 5). Once these input
conditions are met, a command can be issued to the
device.
The reversible software commands are initiated similarly
to a normal byte write operation; however, the slave
device address begins with the bit values 0110. The
next three bits are A2 = 0, A1 = 0 or 1, and A0 = 1, so
that they logically match the values on the input pins. If
the last bit of the slave device address (R/W) is 0, the
RSWP flag can be Cleared or Set. If R/W is 1, the flag
can be verified with the Read SWP command. Following
this bit, the device responds with either ACK or NoACK,
depending on the exact command and the flag status
(see Table 1: Reversible Instructions). To complete the
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev.00D
03/21/06
5
datasheet pdf - http://www.DataSheet4U.net/
5 Page 
IS34C02B
ISSI ®
Figure 7. Page Write
SDA
Bus
Activity
S
T
A
R
T
M
S
B
Device
Address
W
R
I
T
E*
Word Address (n) *
AA
CC
KK
L
S
B
R/W
Data (n)
*
A
C
K
Data (n+1)
*
A
C
K
Data (n+15)
S
T
O
*P
A
C
K
* Acknowledges provided by the slave regardless of hardware or software Write Protection.
Figure 8. Current Address Read
S
T
A
R Device
T Address
SDA
Bus
Activity
M
S
B
R
E
A
D
A
C
K
L
http://www.DataSheet4U.net/
S
B
R/W
Data
S
T
O
P
N
O
A
C
K
Figure 9. Random Address Read
SDA
Bus
Activity
S
T
A
R
T
M
S
B
Device
Address
W
R
I
T
E
A
C
K
L
S
B
R/W
Word
Address (n)
DUMMY WRITE
S
T
A
R
T
A
C
K
Device
Address
R
E
A
D
A
C
K
Data n
S
T
O
P
N
O
A
C
K
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev.00D
03/21/06
11
datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet IS34C02B.PDF ] | |
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