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PDF HT82J30R Data sheet ( Hoja de datos )
| Número de pieza | HT82J30R | |
| Descripción | 16-Channel A/D MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
HT82J30R/HT82J30A
16 Channel A/D MCU with SPI Interface
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V crystal clock mode
· fSYS=12MHz: 2.7V~3.7V RC clock mode
· 35 bidirectional I/O lines (max.)
· 2 interrupt inputs shared with I/O lines
· 8-bit programmable timer/event counter with overflow
interrupt and 7-stage prescaler
· On-chip crystal and RC oscillator
· Watchdog Timer
· 4096´15 program memory ROM
· 216´8 data memory RAM
· PFD function for sound generation
· HALT function and wake-up feature reduces power
consumption
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
General Description
The HT82J30R/HT82J30A are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for A/D applications that interface directly to
analog signals, such as those from sensors.
The mask version HT82J30A is fully pin and functionally
compatible with the OTP version HT82J30R device.
The advantages of low power consumption, I/O flexibil-
ity, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, Pulse
Width Modulation function, Watchdog timer, SPI
· 6-level subroutine nesting
· 16 channel 8-bit resolution A/D converter
· 1 channel (6+2)-bit PWM output shared with an I/O
line
· Bit manipulation instruction
· 15-bit table read instruction
· 63 powerful instructions
· LVR reset voltage of 3V±0.3V
· All instructions executed in one or two machine
cycles
· PB2, PB3, PD4, PD7 can be optioned as either
CMOS or NMOS outputs
· Integrated dual SPI interfaces
· 28-pin SKDIP/SOP and 44-pin QFP packages
interfaces, Power Down and wake-up functions, en-
hance the versatility of these devices to suit a wide
range of A/D application possibilities such as sensor
signal processing, motor driving, industrial control, con-
sumer products, subsystem controllers, etc. With the
provision of dual SPI interfaces the devices are espe-
cially suitable for Joystick Encoder applications.
The HT82J30A is under development and will be avail-
able soon.
Rev. 1.00
1 December 20, 2006
1 page  
www.DataSheet4U.com
A.C. Characteristics
Symbol
Parameter
fSYS1
System Clock
(Crystal OSC)
fSYS2
System Clock
(RC OSC)
fTIMER
Timer I/P Frequency
(TMR)
tWDTOSC Watchdog Oscillator Period
tWDT1
Watchdog Time-out Period
(WDT OSC)
tWDT2
Watchdog Time-out Period
(System Clock)
tRES
External Reset Low Pulse
Width
tSST System Start-up Timer Period
tINT Interrupt Pulse Width
tAD A/D Clock Period
tADC A/D Conversion Time
tADCS A/D Sample Time
tCS_SK SPI SCS to SCK Time
tSPICK SPI Clock Time
Note: *tSYS= 1/fSYS1 or 1/fSYS2
Test Conditions
VDD Conditions
¾ 2.2V~5.5V
¾ 3.3V~5.5V
¾ 2.2V~2.6V
¾ 2.7V~5.5V
¾ 2.2V~5.5V
¾ 3.3V~5.5V
3V ¾
5V ¾
¾¾
¾¾
¾¾
¾ Wake-up from HALT
¾¾
¾¾
¾¾
¾¾
¾¾
¾¾
HT82J30R/HT82J30A
Ta=25°C
Min. Typ. Max. Unit
400
400
1000
1000
0
0
45
32
215
¾ 4000
¾ 8000
¾ 4000
12000 14000
¾ 4000
¾ 8000
90 180
65 130
kHz
kHz
kHz
kHz
kHz
kHz
ms
ms
¾ 216 tWDTOSC
217 ¾ 218 *tSYS
1¾
¾ 1024
1¾
1¾
¾ 76
¾ 32
50 ¾
400 ¾
¾
¾
¾
¾
¾
¾
¾
¾
ms
tSYS
ms
ms
tAD
tAD
ns
ns
Rev. 1.00
5 December 20, 2006
5 Page 
www.DataSheet4U.com
HT82J30R/HT82J30A
prevent the requested interrupt from being serviced.
Once the interrupt request flags (TF, EIF, ADF) are set,
they will remain in the INTC register until the interrupts
are serviced or cleared by a software instruction.
It is recommended that a program does not use the CALL
subroutine within the interrupt subroutine. Interrupts of-
ten occur in an unpredictable manner or need to be ser-
viced immediately in some applications. If only one stack
is left and enabling the interrupt is not well controlled, the
original control sequence will be damaged if a ²CALL² in-
struction is executed in the interrupt subroutine.
Oscillator configuration
There are 2 oscillator circuits in the microcontroller.
V DD
C1
O SC1
R O SC
O SC1
C2
O SC2
R1
fS Y S /4
O SC2
C r y s ta l O s c illa to r N M O S o p e n d r a in R C O s c illa to r
System Oscillator
Both of them are designed for system clocks, namely
the external RC oscillator, the external Crystal oscillator
and the internal RC oscillator, the choice of which is de-
termined by configuration options. The Power Down
mode stops the system oscillator to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VDD is required and the resistance must
range from 47kW to 750kW. The system clock, divided
by 4, is available on OSC2, which can be used to syn-
chronize external logic. The RC oscillator provides the
most cost effective solution. However, the oscillation
frequency may vary with VDD, temperature and pro-
cess variations. It is, therefore, not suitable for timing
sensitive operations where an accurate oscillator fre-
quency is desired.
If the Crystal oscillator is used, a crystal across OSC1 and
OSC2 is needed to provide the feedback and phase shift
required for the oscillator. No other external components
are required. Instead of a crystal, a resonator can also be
connected between OSC1 and OSC2 to obtain a fre-
quency reference, but two external capacitors connected
between OSC1 and OSC2 and ground are required.
The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the sys-
tem enters the power down mode, the system clock is
stopped, but the WDT oscillator still works within a period
of 65ms at 5V. The WDT oscillator can be disabled by op-
tions to conserve power.
Watchdog Timer - WDT
The clock source of WDT is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4), chosen via a configuration op-
tion. This timer is designed to prevent software
malfunctions or the program jumping to unknown loca-
tions. The Watchdog Timer can be disabled by a config-
uration option. If the Watchdog Timer is disabled, all the
executions related to the WDT result in no operation.
If the internal oscillator, which is an RC oscillator with a
nominal period of 65ms at 5V, is selected, it is first di-
vided by 32768~65536 to get a time-out period of ap-
proximately 2.1s~4.3s. This time-out period may vary
with temperature, VDD and process variations. If the
WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT instruction will stop the system
clock.
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². But in the
Power-down mode, the overflow will initialize a ²warm
reset², and only the program counter and the SP are re-
set to zero. To clear the contents of the WDT, three
methods are adopted; an external reset (a low level on
the RES pin), a software instruction or a HALT instruc-
tion. The software instructions include ²CLR WDT² and
the other set - ²CLR WDT1² and ²CLR WDT2². Of these
two types of instruction, only one can be active depend-
ing on the configuration option - ²CLR WDT times selec-
tion option². If the ²CLR WDT² is selected (i.e. CLR
WDT times equal one), any execution of the ²CLR
WDT² instruction will clear the WDT. In the case that
²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLR
WDT times equal two), these two instructions must be
executed to clear the WDT; otherwise, the WDT may re-
set the chip as a result of a time-out.
S y s te m C lo c k /4
O p tio n
fS
8 - b it C o u n te r
S e le c t
7 - b it C o u n te r
T
T
W D T T im e - o u t
fS /2 15~ fS /2 16
W D T C LR W D T
O SC
Watchdog Timer
Rev. 1.00
11 December 20, 2006
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT82J30R.PDF ] | |
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