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PDF HT48R02 Data sheet ( Hoja de datos )

Número de pieza HT48R02
Descripción (HT48R01 - HT48R03) 10-Pin MSOP I/O Type 8-Bit OTP MCU
Fabricantes Holtek Semiconductor 
Logotipo Holtek Semiconductor Logotipo



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HT48R01/HT48R02/HT48R03
10-Pin MSOP I/O Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series
- HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series
- HA0049E Read and Write Control of the HT1380
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
fSYS=12MHz: 4.5V~5.5V
· 7 bidirectional I/O lines and 1 input
· Interrupt input shared with I/O line
· 4 oscillator configuration options
- External crystal OSC
- External RC OSC
- Internal RC+I/O (PA5, PA6)
- Internal RC+RTC OSC (32768Hz)
· Internal RC oscillator
- 3 frequency selections: 4MHz/8MHz/12MHz
- 4MHz with ±10% variation (2.2V~5.5V, 25°C)
- 8MHz with ±10% variation (3.3V~5.5V, 25°C)
- 12MHz with ±10% variation (4.5V~5.5V, 25°C)
· Watchdog Timer
· Program memory ROM: Up to 4096´15
· Data memory RAM: Up to 160´8
· Buzzer driving pair and PFD supported
· Power-down and wake-up functions reduce power
consumption
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· All instructions executed within one or two machine
cycles
· 14-bit or 15-bit table read instruction
· Up to 8-levels of subroutine nesting
· Bit manipulation instruction
· Low voltage reset function
· 10-pin MSOP package
General Description
The HT48R01/HT48R02/HT48R03 are 8-bit high per-
formance, RISC architecture microcontroller devices
specifically designed for I/O control.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, Power-down and
wake-up functions, Watchdog Timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Selection Table
Part No. VDD
Program Data
Memory Memory
HT48R01 2.2V~5.5V 1K´14
64´8
HT48R02 2.2V~5.5V 2K´14
96´8
HT48R03 2.2V~5.5V 4K´15 160´8
I/O
7 I/O,
1 Input
7 I/O,
1 Input
7 I/O,
1 Input
Timer
External
Interrupt
Buzzer
Stack
Package
Types
8-bit´1
1
Ö 4 10MSOP
8-bit´2
1
Ö 6 10MSOP
8-bit´2
1
Ö 8 10MSOP
Rev. 1.00
1 December 20, 2006

1 page




HT48R02 pdf
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HT48R01/HT48R02/HT48R03
A.C. Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
VDD Conditions
fSYS1
System Clock
(Crystal OSC, RC OSC)
¾ 2.2V~5.5V
¾ 3.3V~5.5V
¾ 4.5V~5.5V
4.5V~
5.5V
12MHz, Ta=25°C
fSYS2
System Clock (Internal RC OSC)
(±10%)
3.3V~
5.5V
8MHz, Ta=25°C
2.2V~
5.5V
4MHz, Ta=25°C
fSYS3
System Clock (32768 Crystal)
¾
¾
¾ 2.2V~5.5V
fTIMER
Timer I/P Frequency (TMR)
¾ 3.3V~5.5V
¾ 4.5V~5.5V
Min. Typ. Max. Unit
400 ¾ 4000 kHz
400 ¾ 8000 kHz
400 ¾ 12000 kHz
10800 12000 13200 kHz
7200 8000 8800 kHz
3600 4000 4400 kHz
¾ 32768 ¾
Hz
0 ¾ 4000 kHz
0 ¾ 8000 kHz
0 ¾ 12000 kHz
tWDTOSC Watchdog Oscillator Period
3V
5V
¾
¾
45 90 180 ms
32 65 130 ms
tRES External Reset Low Pulse Width ¾
¾
1 ¾ ¾ ms
tSST
System Start-up Timer Period
¾ Wake-up from HALT ¾ 1024 ¾
tSYS
tINT Interrupt Pulse Width
¾¾
1 ¾ ¾ ms
tLVR Low Voltage Width to Reset
¾
¾
0.25
1
2 ms
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
¾ ¾ 100 mV
RPOR
VDD Rise Rate to Ensure
Power-on Reset
¾
¾
0.035 ¾
¾ V/ms
Note: tSYS=1/fSYS1, 1/fSYS2 or 1/fSYS3
Rev. 1.00
5 December 20, 2006

5 Page





HT48R02 arduino
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HT48R01/HT48R02/HT48R03
The internal timer/event counter interrupt is initialised by
setting the timer/event counter interrupt request flag
(TF; bit 5 of INTC), caused by a timer overflow. When
the interrupt is enabled, the stack is not full and the TF
bit is set, a subroutine call to location 08H will occur. The
related interrupt request flag,TF, will be reset and the
EMI bit cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the ²RETI²
instruction is executed or the EMI bit and the related in-
terrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, ²RET²
or ²RETI² may be invoked. RETI will set the EMI bit to en-
able an interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority Vector
External Interrupt
1 04H
Timer/Event Counter 0 Overflow 2
08H
Interrupt Subroutine Vector for HT48R01
Interrupt Source
Priority Vector
External Interrupt
1 04H
Timer/Event Counter 0 Overflow 2
08H
Timer/Event Counter 1 Overflow 3
0CH
Interrupt Subroutine Vector for HT48R02/HT48R03
Once the interrupt request flags (T0F/ T1F, EIF) are set,
they will remain in the INTC register until the interrupts
are serviced or cleared by a software instruction. It is
recommended that a program does not use the ²CALL
subroutine² within the interrupt subroutine. Interrupts
often occur in an unpredictable manner or need to be
serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well con-
trolled, the original control sequence will be damaged
once the ²CALL² operates in the interrupt subroutine.
Oscillator Configuration
There are 4 different oscillator modes implemented in
the microcontroller, which are selected by configuration
options. All of them are designed for system clocks,
namely the external RC oscillator (ERC), external crys-
tal oscillator (ECRY), internal RC oscillator with I/O(IRC)
and internal RC oscillator with RTC OSC (IRC+RTC).
No matter what oscillator type is selected, the signal
provides the system clock. The Power-down mode
stops the system oscillator, except for the RTC oscilla-
tor, and resists external signals to conserve power.
Bit No.
0
1
2
3, 6~7
4
5
Label
EMI
EEI
ET0I
¾
EIF
T0F
Function
Controls the master (global) interrupt (1= enabled; 0= disabled)
Controls the external interrupt (1= enabled; 0= disabled)
Controls the timer/event counter 0 interrupt (1= enabled; 0= disabled)
Unused bit, read as ²0²
External interrupt request flag (1= active; 0= inactive)
Internal timer/event counter 0 request flag (1= active; 0= inactive)
INTC 0 (0BH) Register for HT48R01
Bit No.
0
1
2
3
4
5
5
7
Label
EMI
EEI
ET0I
ET1I
EIF
T0F
T1F
¾
Function
Controls the master (global) interrupt (1= enabled; 0= disabled)
Controls the external interrupt (1= enabled; 0= disabled)
Controls the timer/event counter 0 interrupt (1= enabled; 0= disabled)
Controls the timer/event counter 1 interrupt (1= enabled; 0= disabled)
External interrupt request flag (1= active; 0= inactive)
Internal timer/event counter 0 request flag (1= active; 0= inactive)
Internal timer/event counter 1 request flag (1= active; 0= inactive)
Unused bit, read as ²0²
INTC 0 (0BH) Register for HT48R02/HT48R03
Rev. 1.00
11 December 20, 2006

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