PDF MT9161B Data sheet ( Hoja de datos )

Número de pieza	MT9161B
Descripción	(MT9160B / MT9161B) 5 Volt Multi-Featured Codec
Fabricantes	Zarlink Semiconductor
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No Preview Available ! www.DataSheet4U.com ISO2-CMOS MT9160B/61B 5 Volt Multi-Featured Codec (MFC) Advance Information Features • Improved idle channel noise over MT9160 • MT9161 version features a delayed framing pulse in SSI and ST-BUS modes to facilitate cascaded devices • Programmable µ-Law/A-Law Codec and Filters • Programmable ITU-T G.711/sign-magnitude coding • Programmable transmit, receive and side-tone gains • Fully differential interface to handset transducers - including 300 ohm receiver driver • Flexible digital interface including ST-BUS/SSI • Serial microport or default controllerless mode • Single 5 volt supply • Low power operation • ITU-T G.714 compliant Applications • Digital telephone sets • Cellular radio sets • Local area communications stations DS5145 ISSUE 3 March 1999 Ordering Information MT9161BE MT9160BE MT9161BS MT9160BS MT9161BN MT9160BN 24 Pin Plastic DIP(600 mil) 24 Pin Plastic DIP(600 mil) 24 Pin SOIC 20 Pin SOIC 24 Pin SSOP 20 Pin SSOP -40°C to +85°C Description The MT9160B/61B 5V Multi-featured Codec incorporates a built-in Filter/Codec, gain control and programmable sidetone path as well as on-chip anti-alias ﬁlters, reference voltage and bias source. The device supports both ITU-T and sign-magnitude A-Law and µ-Law requirements. Complete telephony interfaces are provided for connection to handset transducers. Internal register access is provided through a serial microport compatible with various industry standard micro-controllers. The device also supports controllerless operation utilizing the default register conditions. The MT9160B/61B is fabricated in Zarlink's ISO2-CMOS technology ensuring low power consumption and high reliability. VSSD VDD VSSA VBias VRef Din Dout STB/F0i CLOCKin STBd/FOod (MT9161B only) FILTER/CODEC GAIN ENCODER 7dB DECODER -7dB Transducer Interface Flexible Digital Interface Timing ST-BUS C&D Channels Serial Microport PWRST IC CS DATA1 DATA2 SCLK Figure 1 - Functional Block Diagram M- M+ HSPKR + HSPKR - A/µ/IRQ 79 1 page Advance Information MT9160B/61B Serial Port PCM Din Decoder 2.05dB Filter/Codec and Transducer Interface Default Bypass Receive Filter Gain 0 to -7 dB (1 dB steps) -6 dB -8.05 dB or -2.05 dB Receiver Driver Side-tone -9.96 to +9. 96 dB (3.32 dB steps) HSPKR + 75Ω HSPKR - 75Ω -11 dB Handset Receiver (150Ω) PCM Dout Encoder -2.05dB TTrraannssmmititFFiltieltrer GGaainin (010 dttooB++s7t7edpBds)B (1 dB steps) Transmit Gain -0.37 dB or 8.93 dB Transmit Gain 8.42 dB M+ Transmitter M- Microphone INTERNAL TO DEVICE Figure 3 - Audio Gain Partitioning EXTERNAL TO DEVICE (DATA2), a chip select pin (CS) and a synchronous data clock pin (SCLK). For D-channel contention control, in ST-BUS mode, this interface provides an open-drain interrupt output (IRQ). The microport dynamically senses the state of the serial clock (SCLK) each time chip select becomes active. The device then automatically adjusts its internal timing and pin conﬁguration to conform to Intel or Motorola/National requirements. If SCLK is high during chip select activation then Intel mode 0 timing is assumed. The DATA1 pin is deﬁned as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK is low during chip select activation then Motorola/National timing is assumed. Motorola processor mode CPOL=0, CPHA=0 must be used. DATA1 is deﬁned as the data transmit pin while DATA2 becomes the data receive pin. Although the dual port Motorola controller conﬁguration usually supports full-duplex communication, only half-duplex communication is possible in the MT9160B/61B. The micro must discard non-valid data which it clocks in during a valid write transfer to the MT9160B/61B. During a valid read transfer from the MT9160B/61B data simultaneously clocked out by the micro is ignored by the MT9160B/61B. All data transfers through the microport are two-byte transfers requiring the transmission of a Command/ Address byte followed by the data byte written or read from the addressed register. CS must remain asserted for the duration of this two-byte transfer. As shown in Figures 5 and 6 the falling edge of CS indicates to the MT9160B/61B that a microport transfer is about to begin. The ﬁrst 8 clock cycles of SCLK after the falling edge of CS are always used to receive the Command/Address byte from the microcontroller. The Command/Address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock cycles are used to transfer the data byte between the MT9160B/61B and the microcontroller. At the end of the two-byte transfer CS is brought high again to terminate the session. The rising edge of CS will tri-state the output driver of DATA1 which will remain tri-stated as long as CS is high. Intel processors utilize least signiﬁcant bit ﬁrst transmission while Motorola/National processors employ most signiﬁcant bit ﬁrst transmission. The MT9160B/61B microport automatically accommodates these two schemes for normal data bytes. However, to ensure decoding of the R/W and address information, the Command/Address byte is deﬁned differently for Intel operation than it is for 83 5 Page MT9160B/61B Advance Information Register Summary Address 00 01 02 03 04 05 06 07y Bit 7 RxINC - - PDFDI CEN C7 D7 - Bit 6 RxFG2 Bit 5 RxFG1 Bit 4 RxFG0 Bit 3 TxINC Bit 2 TxFG2 Bit 1 TxFG1 --- - STG2 STG1 - PDDR - RST - - -- - TxMute RxMute TxBsel DEN C6 D8 C5 A/µ Smag/ CSL2 CSL1 ITU-T C4 C3 C2 C1 D6 D5 D4 D3 D2 D1 - - - PCM/ loopen - ANALOG Table 2 - 5V Multi-featured Codec Register Map Bit 0 TxFG0 STG0 DrGain RxBsel CSL0 C0 D0 - Description Gain Control Register 1 Gain Control Register 2 Path Control Control Register 1 Control Register 2 C-Channel Register D-Channel Register Loop Back Gain Control Register 1 ADDRESS = 00h WRITE/READ VERIFY RxINC RxFG2 RxFG1 RxFG0 TxINC TxFG2 TxFG1 TxFG0 76543210 Power Reset Value 1000 0000 Receive Gain Setting (dB) (default) 0 -1 -2 -3 -4 -5 -6 -7 RxFG2 0 0 0 0 1 1 1 1 RxFGn = Receive Filter Gain bit n RxFG1 0 0 1 1 0 0 1 1 RxFG0 0 1 0 1 0 1 0 1 Transmit Gain Setting (dB) (default) 0 1 2 3 4 5 6 7 TxFG2 0 0 0 0 1 1 1 1 TxFGn = Transmit Filter Gain bit n RxINC: When high, the receive path nominal gain is set to 0 dB. When low, this gain is -6.0 dB. TxINC: When high, the transmit nominal gain is set to 15.3 dB. When low, this gain is 6.0 dB. TxFG1 0 0 1 1 0 0 1 1 TxFG0 0 1 0 1 0 1 0 1 Note: Bits marked "-" are reserved bits and should be written with logic "0" 89 11 Page

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