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ISL90726 の電気的特性と機能

ISL90726のメーカーはIntersil Corporationです、この部品の機能は「Digitally Controlled Potentiometer」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL90726
部品説明 Digitally Controlled Potentiometer
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL90726 Datasheet, ISL90726 PDF,ピン配置, 機能
®
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Data Sheet
ISL90726
Single Volatile 128-Tap XDCP
August 3, 2005
FN8244.1
Digitally Controlled Potentiometer
(XDCP™)
The Intersil ISL90726 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, and a control section. The wiper position is
controlled by an I2C interface.
The potentiometer is implemented by a resistor array
composed of 127 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the SDA and SCL inputs.
The device can be used in a wide variety of applications
including:
• Mechanical potentiometer replacement
• Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
• Laser diode and LED biasing
• LCD brightness and contrast adjustment
• Gain control and offset adjustment
Ordering Information
PART NUMBER
(See Note)
ISL90726WIE6Z
RESISTANCE
OPTION ()
TEMP
RANGE
(°C)
10K -40 to +85
PACKAGE
(Pb-Free)
6-Pin SC-70
ISL90726UIE6Z
50K -40 to +85 6-Pin SC-70
ISL90726WIE6Z-TK
10K
-40 to +85 6-Pin SC-70
ISL90726UIE6Z-TK 50K -40 to +85 6-Pin SC-70
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Volatile Solid-State Potentiometer
• I2C Serial Bus Interface
• DCP Terminal Voltage, 2.7V to 5.5V
• Low Tempco
- Rheostat - 45 ppm/°C typical @ 25°C
- Divider - 15 ppm/°C typical @ 25°C
• 128 Wiper Tap Points
- Wiper resistance 70typ at VCC = 3.3V
• Low Power CMOS
- Active current, 200µA max
- Standby current, 500nA max
• Available RTOTAL Values = 50kΩ, 10k
• Power on Preset to Midscale
• Direct replacement for AD5246
• Packaging
- 6 Ld SC70
• Pb-free plus anneal available (RoHS compliant)
Pinout
ISL90726
(6-PIN SC70)
TOP VIEW
VDD 1
GND 2
SCL 3
6 RL
5 RW
4 SDA
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL90726 pdf, ピン配列
ISL90726
Absolute Maximum Ratings
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any digital interface pin
with respect to VSS . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Voltage at any DCP pin with
respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC
Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level B at 85°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV Human Body Model
Recommended Operating Conditions
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Power rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications Over recommended operating conditions unless otherwise stated.
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 1) MAX
UNIT
RTOTAL
RW (Note 10)
CH/CL/CW
(Note 10)
RH to RL resistance
RH to RL resistance tolerance
Wiper resistance
Potentiometer Capacitance
W, U versions respectively
VCC = 3.3V @25°C
10, 50
-20 +20
85
10/10/
25
k
%
pF
ILkgDCP
Leakage on DCP pins
RESISTOR MODE
Voltage at pin from GND to VCC
0.1 1 µA
RINL
(Note 8)
Integral non-linearity
DCP register set between 20 hex and 7F hex.
Monotonic over all tap positions
-2
±0.25
2 MI
(Note 5)
RDNL (Note 7) Differential non-linearity
DCP register set between 20 hex W option -1 ±0.1 1
MI
and 7F hex. Monotonic over all tap
(Note 5)
positions
U option
-1
±0.1
1
MI
(Note 5)
Roffset
(Note 6)
Offset
W option
0 1 3 MI
(Note 5)
U option
0 0.5 2 MI
(Note 5)
TCR
Resistance Temperature Coefficient DCP register set between 20 hex and 7F hex
(Notes 9, 10)
±45 ppm/°C
Operating Specifications
SYMBOL
PARAMETER
ICC1
VCC supply current
(Volatile write/read)
ISB VCC current (standby)
IComLkg Common-Mode Leakage
tDCP (Note 10) DCP wiper response time
VCCRamp
tD
VCC ramp rate
Power-up delay
TEST CONDITIONS
TYP
MIN (Note 1) MAX
fSCL = 400kHz; SDA = Open; (for I2C, Active,
Read and Volatile Write States only)
200
VCC = +5.5V, I2C Interface in Standby State
500
Voltage at SDA pin at GND or VCC
3
SCL falling edge of last bit of DCP Data Byte to
wiper change
500
0.2
VCC above Vpor,
recall completed,
to DCP Initial Value
and I2C Interface in
Register
standby
state
3
UNIT
µA
nA
µA
ns
V/ms
ms
3 FN8244.1
August 3, 2005


3Pages


ISL90726 電子部品, 半導体
ISL90726
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 1). On power-up of the ISL90726, the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90726 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 1). A START condition is ignored during the power-up
sequence and during internal non-volatile write cycles.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 1).
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 2).
The ISL90726 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL90726 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 0101000 as the seven
MSBs. The LSB in the Read/Write bit. Its value is “1” for a
Read operation, and “0” for a Write operation (See Table 1).
TABLE 1. IDENTIFICATION BYTE FORMAT
0 1 0 1 0 0 0 R/W
(MSB)
(LSB)
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90726 responds with an ACK. At this time, the device
enters its standby state (See Figure 3).
Data Protection
A valid Identification Byte, Address Byte, and total number of
SCL pulses act as a protection of both volatile and non-
volatile registers. During a Write sequence, the Data Byte is
loaded into an internal shift register as it is received. If the
Address Byte is 0h, the Data Byte is transferred to the Wiper
Register (WR) at the falling edge of the SCL pulse that loads
the last bit (LSB) of the Data Byte. If an address other than
00h, or an invalid slave address is sent, then the device will
respond with no ACK.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 4). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL90726 responds with an ACK. Then the ISL90726
transmits the Data Byte as long as the master responds with
an ACK during the SCL cycle following the eighth bit of each
byte. The master then terminates the read operation (issuing
a STOP condition) following the last bit of the Data Byte (See
Figure 4).
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
STOP
FIGURE 1. VALID DATA CHANGES, START, AND STOP CONDITIONS
6 FN8244.1
August 3, 2005

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共有リンク

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