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PDF TSC87C51 Data sheet ( Hoja de datos )
| Número de pieza | TSC87C51 | |
| Descripción | CMOS 0 to 25 MHz Programmable 8-bit Microcontroller | |
| Fabricantes | TEMIC Semiconductors | |
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TSC87C51
CMOS 0 to 25 MHz Programmable 8–bit Microcontroller
Description
TEMIC’s TSC87C51 is high performance CMOS
EPROM version of the 80C51 CMOS single chip 8 bit
microcontroller.
The fully static design of the TSC87C51 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TSC87C51 retains all the features of the 80C51 with
some enhancement: 4 K bytes of internal code memory
(EPROM); 128 bytes of internal data memory (RAM);
32 I/O lines; two 16 bit timers; a 5-source, 2-level
interrupt structure; a full duplex serial port with framing
error detection; a power off flag; and an on-chip
oscillator.
The TSC87C51 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM, the timers, the serial port and the interrupt
system continue to function. In the power down mode
the RAM is saved and all other functions are inoperative.
The TSC87C51 is manufactured using non volatile
SCMOS process which allows it to run up to:
D 25 MHz with VCC = 5 V ± 10%.
Features
D 4 Kbytes of EPROM
G Improved Quick Pulse programming algorithm
G Secret ROM by encryption
D 128 bytes of RAM
D 64 Kbytes program memory space
D 64 Kbytes data memory space
D 32 programmable I/O lines
D Two 16 bit timer/counters
D Programmable serial port with framing error
detection
D Power control modes
D Two–level interrupt priority
D Fully static design
D 0.8µ SCMOS non volatile process
D ONCE Mode
D Enhanced Hooks system for emulation purpose
D Military temperature ranges (–55oC to + 125oC)
D Available packages:
G CDIL40 (OTP)
G CDIL40 (UV erasable)
G CQPJ44 (OTP)
G CQPJ44 (UV erasable)
Rev. E – July 03, 2000
1
1 page  
TSC87C51
Port 3 also serves the functions of various special features of the TEMIC’s C51 Family, as listed below:
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Function
RxD (serial input port)
TxD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (Timer 0 external input)
T1 (Timer 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
Port 3 can sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups.
Some Port 3 pins receive control signals during EPROM programming and program verification.
RST
A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal pull-down
resistor permits Power-On reset using only a capacitor connected to VCC. The port pins will be driven to their reset
condition when a minimum VIH1 voltage is applied whether the oscillator is started or not (asynchronous reset).
ALE/PROG
Address Latch Enable output for latching the low byte of the address during accesses to external memory. ALE is
activated as though for this purpose at a constant rate of 1/6 the oscillator frequency except during an external data
memory access at which time one ALE pulse is skipped.
ALE can sink/source 8 LS TTL inputs. It can drive CMOS inputs without external pullup.
If desired, to reduce EMI, ALE operation can be disabled by setting bit 0 of SFR location 8Eh (MSCON). With this
bit set, the pin is weakly pulled high. However, ALE remains active during MOVX, MOVC instructions and external
fetches. Setting the ALE disable bit has no effect if the microcontroller is in external execution mode (EA=0).
Throughout the remainder of this datasheet, ALE will refer to the signal coming out of the ALE/PROG pin, and the
pin will be referred to as the ALE/PROG pin.
PSEN
Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory. (However, when executing out of external Program Memory, two
activations of PSEN are skipped during each access to external Data Memory). PSEN is not activated during fetches
from internal Program Memory. PSEN can sink/source 8 LS TTL inputs. It can drive CMOS inputs without an external
pullup.
EA/VPP
External Access enable. EA must be strapped to VSS in order to enable the device to fetch code from external Program
Memory locations 0000h to FFFFh. Note however, that if any of the Security bits are programmed, EA will be internally
latched on reset.
EA should be strapped to VCC for internal program execution.
This pin also receives the programming supply voltage (VPP) during EPROM programming.
XTAL1
Input to the inverting amplifier that forms the oscillator. Receives the external oscillator signal when an external
oscillator is used.
XTAL2
Output from the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator
is used.
Rev. E – July 03, 2000
5
5 Page 
TSC87C51
PROGRAM
SIGNALS*
CONTROL
SIGNALS*
EA/VPP
ALE/PROG
RST
PSEN
P2.6
P2.7
P3.3
P3.6
P3.7
+5V
VCC
P0.0–P0.7
D0–D7
P1.0–P1.7
P2.0–P2.3
A0–A7
A8–A11
4 to 6 MHz
XTAL1
* See Table 5 for proper value on these inputs
VSS
GND
Figure 6 Set–up modes configuration
Programming algorithm
The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses applied
during byte programming from 25 to 5.
To program the TSC87C51 the following sequence must be exercised:
D Step 1: Input the valid address on the address lines.
D Step 2: Input the appropriate data on the data lines.
D Step 3: Activate the combination of control signals.
D Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V).
D Step 5: Pulse ALE/PROG 5 times.
Repeat step 1 through 5 changing the address and data for the entire array or until the end of the object file is reached
(see Figure 7).
Verify algorithm
Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of
the programmed array will ensure reliable programming of the TSC87C51.
To verify the TSC87C51 code the following sequence must be exercised :
D Step 1: Activate the combination of program signals.
D Step 2: Input the valid address on the address lines.
D Step 3: Input the appropriate data on the data lines.
D Step 4: Activate the combination of control signals.
Repeat step 2 through 4 changing the address and data for the entire array (see Figure 7).
The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the code
array is well encrypted.
Rev. E – July 03, 2000
11
11 Page | ||
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