|
|
PDF MT28F322D18 Data sheet ( Hoja de datos )
| Número de pieza | MT28F322D18 | |
| Descripción | (MT28F322D18 / MT28F322D20) FLASH MEMORY | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MT28F322D18 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
FLASH MEMORY
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
MT28F322D20
MT28F322D18
Low Voltage, Extended Temperature
0.18µm Process Technology
FEATURES
• Flexible dual-bank architecture
– Support for true concurrent operation with zero
latency
– Read bank a during program bank b and vice versa
– Read bank a during erase bank b and vice versa
• Basic configuration:
Seventy-one erasable blocks
– Bank a (8Mb for data storage)
– Bank b (24Mb for program storage)
• VCC, VCCQ, VPP voltages
– 1.70V (MIN), 1.90V (MAX) VCC, VCCQ
(MT28F322D18 only)
– 1.80V VCC, VCCQ (MIN); 2.20V VCC (MAX)and 2.25V
VCCQ (MAX) (MT28F322D20 only)
– 0.9V (TYP) VPP (in-system PROGRAM/ERASE)
– 12V ±5% (HV) VPP tolerant (factory programming
compatibility)
• Random access time: 70ns/80ns @ 1.70V VCC
• Burst Mode read access (MT28F322D20)
– MAX clock rate: 54 MHz (tCLK = 18.5ns)
– Burst latency: 70ns @ 1.80V VCC and 54 MHz
– tACLK: 17ns @ 1.80V VCC and 54 MHz
• Page Mode read access1
– Eight-word page
– Interpage read access: 70ns/80ns @ 1.80V
– Intrapage read access: 30ns @ 1.80V
• Low power consumption (VCC = 2.20V)
– Asynchronous READ < 15mA (MAX)
– Standby < 50µA
– Automatic power saving feature (APS)
• Enhanced write and erase suspend options
– ERASE-SUSPEND-to-READ within same bank
– PROGRAM-SUSPEND-to-READ within same bank
– ERASE-SUSPEND-to-PROGRAM within same bank
• Dual 64-bit chip protection registers for security
purposes
• Cross-compatible command support
– Extended command set
– Common flash interface
• PROGRAM/ERASE cycle
– 100,000 WRITE/ERASE cycles per block
NOTE: 1. Data based on MT28F322D20 device.
2. A “5” in the part mark represents two different
frequencies: 54 MHz (MT28F322D20) or 52 MHz
(MT28F322D18)
BALL ASSIGNMENT
58-Ball FBGA
12345678
A A11 A8 VSS VCC VPP A18 A6 A4
B
A12 A9
A20 CLK RST# A17
A5
A3
C A13 A10
ADV# WE# A19
A7
A2
D A15 A14 WAIT# A16 DQ12 WP#
A1
E VCCQ DQ15 DQ6 DQ4 DQ2 DQ1 CE# A0
F VSS DQ14 DQ13 DQ11 DQ10 DQ9 DQ0 OE#
G DQ7 VSSQ DQ5 VCC DQ3 VCCQ DQ8 VSSQ
Top View
(Ball Down)
NOTE: See page 7 for Ball Description Table.
See page 43 for mechanical drawing.
OPTIONS
• Timing
70ns access
80ns access
• Frequency
54 MHz
40 MHz
No burst operation
• Boot Block Configuration
Top
Bottom
• Package
58-ball FBGA (8 x 7 ball grid)
• Operating Temperature Range
Extended (-40ºC to +85ºC)
MARKING
-70
-80
52
4
None
T
B
FH
ET
Part Number Example:
MT28F322D20FH-804 BET
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
1
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
1 page  
Block
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Bank b = 24Mb
Block Size
(K-bytes/K-words)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
Figure 2
Bottom Boot Block Device
Address Range
(x16)
1F8000h-1FFFFFh
1F0000h-1F7FFFh
1E8000h-1EFFFFh
1E0000h-1E7FFFh
1D8000h-1DFFFFh
1D0000h-1D7FFFh
1C8000h-1CFFFFh
1C0000h-1C7FFFh
1B8000h-1BFFFFh
1B0000h-1B7FFFh
1A8000h-1AFFFFh
1A0000h-1A7FFFh
198000h-19FFFFh
190000h-197FFFh
188000h-18FFFFh
180000h-187FFFh
178000h-17FFFFh
170000h-177FFFh
168000h-16FFFFh
160000h-167FFFh
158000h-15FFFFh
150000h-157FFFh
148000h-14FFFFh
140000h-147FFFh
138000h-13FFFFh
130000h-137FFFh
128000h-12FFFFh
120000h-127FFFh
118000h-11FFFFh
110000h-117FFFh
108000h-10FFFFh
100000h-107FFFh
0F8000h-0FFFFFh
0F0000h-0F7FFFh
0E8000h-0EFFFFh
0E0000h-0E7FFFh
0D8000h-0DFFFFh
0D0000h-0D7FFFh
0C8000h-0CFFFFh
0C0000h-0C7FFFh
0B8000h-0BFFFFh
0B0000h-0B7FFFh
0A8000h-0AFFFFh
0A0000h-0A7FFFh
098000h-097FFFh
090000h-097FFFh
088000h-087FFFh
080000h-087FFFh
Block
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bank a = 8Mb
Block Size
(K-bytes/K-words)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Address Range
(x16)
078000h-07FFFFh
070000h-077FFFh
068000h-067FFFh
060000h-067FFFh
058000h-05FFFFh
050000h-057FFFh
048000h-04FFFFh
040000h-047FFFh
038000h-03FFFFh
030000h-037FFFh
028000h-02FFFFh
020000h-027FFFh
018000h-01FFFFh
010000h-017FFFh
008000h-00FFFFh
007000h-007FFFh
006000h-006FFFh
005000h-005FFFh
004000h-004FFFh
003000h-003FFFh
002000h-002FFFh
001000h-001FFFh
000000h-000FFFh
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
5 Page 
2 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 5
Command Descriptions
CODE DEVICE MODE BUS CYCLE
DESCRIPTION
10h Alt. Program Setup First
Operates the same as PROGRAM SETUP command
20h Erase Setup
First
Prepares the CSM for the ERASE CONFIRM command. If the next
command is not an ERASE CONFIRM command, the command will be
ignored, and the bank will go to read status mode and wait for
another command.
40h Program Setup
First
A two-cycle command: The first cycle prepares for a PROGRAM
operation, and the second cycle latches addresses and data and
initiates the WSM to execute the program algorithm. The flash outputs
status register data on the rising edge of ADV#, or on the rising clock
edge when ADV# is LOW during synchronous burst mode, or on the
falling edge of OE# or CE#, whichever occurs first.
50h Clear Status
Register
First
The WSM can set the block lock status (SR1), VPP status (SR3), program
status (SR4), and erase status (SR5) bits in the status register to “1,” but
it cannot clear them to “0.” Issuing this command clears those bits to
“0.”
60h Protection
Configuration
Setup
First
Prepares the CSM for changes to the block locking status. If the next
command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK DOWN
the command will be ignored, and the device will go to read status
mode.
Set Read
Configuration
Register
First Puts the device into the set read configuration mode so that it will
be possible to set the option bits related to burst read mode.
70h Read Status
Register
First
This command places the device into a read status register mode.
Reading the device will output the contents of the status register for
the addressed bank. The device will automatically enter this mode for
the addressed bank after a PROGRAM or ERASE operation has been
initiated.
90h Read Protection
Configuration
First
Puts the device into the read protection configuration mode so that
reading the device will output the manufacturer/device codes, block
lock status, protection register, or protection register lock status.
98h Read Query
First Puts the device into the read query mode so that reading the device
will output common flash interface information.
B0h Program/Erase
Suspend
First Issuing this command will suspend the currently executing PROGRAM/
ERASE operation. The status register will indicate when the
operation has been successfully suspended by setting either the
program suspend (SR2) or erase suspend (SR6), and the WSM status bit
(SR7) to a “1” (ready). The WSM will continue to idle in the suspend
state, regardless of the state of all input control signals except RST#,
which will immediately shut down the WSM and the remainder of the
chip if RST# is driven to VIL.
C0h Program Device
Protection Register
First
Writes a specific code into the device protection register.
Lock Device
Protection Register
First
Locks the device protection register; data can no longer be changed.
(continued on next page)
2 Meg x 16 Async/Page/Burst Flash Memory
MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT28F322D18.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MT28F322D18 | (MT28F322D18 / MT28F322D20) FLASH MEMORY | Micron Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |