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Datasheet MC74HC147 PDF ( 特性, スペック, ピン接続図 )

部品番号 MC74HC147
部品説明 Decimal-to-BCD Encoder High-Performance Silicon-Gate CMOS
メーカ Motorola
ロゴ Motorola ロゴ 
プレビュー
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MC74HC147 Datasheet, MC74HC147 PDF,ピン配置, 機能
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Decimal-to-BCD Encoder
High–Performance Silicon–Gate CMOS
MC74HC147
The MC74HC147 is identical in pinout to the LS147. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device encodes nine active–low data inputs to four active–low BCD
Address Outputs, ensuring that only the highest order active data line is
encoded. The implied decimal zero condition is encoded when all nine data
inputs are at a high level (inactive).
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 136 FETs or 34 Equivalent Gates
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
PIN ASSIGNMENT
LOGIC DIAGRAM
DECIMAL
DATA INPUTS
(ACTIVE–LOW)
D1 11
D2 12
D3 13
D4 1
D5 2
D6 3
D7 4
D8 5
D9 10
9 A0
7 A1
6 A2
14 A3
VCC = PIN 16
GND = PIN 8
NO CONNECTION = PIN 15
BCD
ADDRESS
OUTPUTS
(ACTIVE–LOW)
D4 1
D5 2
16 VCC
15 NC
D6 3
D7 4
D8 5
14 A3
13 D3
12 D2
A2 6
11 D1
A1 7
GND 8
10 D9
9 A0
NC = NO CONNECTION
FUNCTION TABLE
Inputs
Outputs
D9 D8 D7 D6 D5 D4 D3 D2 D1 A3 A2 A1 A0
HHHHHHHHHHHHH
HHHHHHHH L HHH L
HHHHHHHL XHHLH
HHHHHHL XXHHL L
HHHHHL XXXHLHH
HHHHL XXXXHLHL
HHHL XXXXXHL LH
HHL XXXXXXHL L L
HL XXXXXXX LHHH
L XXXXXXXX LHHL
10/95
© Motorola, Inc. 1995
1 REV 6

1 Page



MC74HC147 pdf, ピン配列
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
tPHL
Parameter
Maximum Propagation Delay, Input D to Output A
(Figures 1 and 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCin MaximumInputCapacitance
MC74HC147
VCC
V
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
– 55 to
25_ C
v 85_C v 125_C
220 275 330
44 55 66
37 47 56
75 95 110
15 19 22
13 16 19
10 10 10
Unit
ns
ns
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
35 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
INPUT D
tPHL
OUTPUT A
tr
90%
50%
10%
90%
50%
10%
tTHL
tf
VCC
GND
tPLH
tTLH
Figure 1. Switching Waveforms
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 2. Test Circuit
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA


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