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PDF HD6413003TVF Data sheet ( Hoja de datos )
| Número de pieza | HD6413003TVF | |
| Descripción | Microcontroller | |
| Fabricantes | RENESAS | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HD6413003TVF (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
Contents
Section 1 Overview...................................................................................................... 1
1.1 Overview ........................................................................................................................ 1
1.2 Block Diagram................................................................................................................ 5
1.3 Pin Description ............................................................................................................... 6
1.3.1 Pin Arrangement............................................................................................. 6
1.3.2 Pin Functions .................................................................................................. 7
1.4 Pin Functions .................................................................................................................. 11
Section 2 CPU ............................................................................................................... 17
2.1 Overview ........................................................................................................................ 17
2.1.1 Features........................................................................................................... 17
2.1.2 Differences from H8/300 CPU ....................................................................... 18
2.2 CPU Operating Modes.................................................................................................... 19
2.3 Address Space................................................................................................................. 20
2.4 Register Configuration.................................................................................................... 21
2.4.1 Overview......................................................................................................... 21
2.4.2 General Registers............................................................................................ 22
2.4.3 Control Registers ............................................................................................ 23
2.4.4 Initial CPU Register Values ............................................................................ 24
2.5 Data Formats................................................................................................................... 25
2.5.1 General Register Data Formats....................................................................... 25
2.5.2 Memory Data Formats .................................................................................... 26
2.6 Instruction Set................................................................................................................. 28
2.6.1 Instruction Set Overview ................................................................................ 28
2.6.2 Instructions and Addressing Modes................................................................ 29
2.6.3 Tables of Instructions Classified by Function................................................. 30
2.6.4 Basic Instruction Formats ............................................................................... 40
2.6.5 Notes on Use of Bit Manipulation Instructions .............................................. 41
2.7 Addressing Modes and Effective Address Calculation .................................................. 41
2.7.1 Addressing Modes .......................................................................................... 41
2.7.2 Effective Address Calculation ........................................................................ 44
2.8 Processing States ............................................................................................................ 48
2.8.1 Overview......................................................................................................... 48
2.8.2 Program Execution State ................................................................................ 49
2.8.3 Exception-Handling State............................................................................... 49
2.8.4 Exception-Handling Sequences ...................................................................... 51
2.8.5 Bus-Released State ......................................................................................... 52
2.8.6 Reset State ...................................................................................................... 52
2.8.7 Power-Down State .......................................................................................... 52
5 Page 
10.2.11 Timer I/O Control Register (TIOR)................................................................ 310
10.2.12 Timer Status Register (TSR)........................................................................... 312
10.2.13 Timer Interrupt Enable Register (TIER)......................................................... 315
10.3 CPU Interface ................................................................................................................. 317
10.3.1 16-Bit Accessible Registers ............................................................................ 317
10.3.2 8-Bit Accessible Registers .............................................................................. 319
10.4 Operation ........................................................................................................................ 321
10.4.1 Overview......................................................................................................... 321
10.4.2 Basic Functions............................................................................................... 322
10.4.3 Synchronization .............................................................................................. 332
10.4.4 PWM Mode .................................................................................................... 334
10.4.5 Reset-Synchronized PWM Mode ................................................................... 338
10.4.6 Complementary PWM Mode.......................................................................... 341
10.4.7 Phase Counting Mode..................................................................................... 351
10.4.8 Buffering......................................................................................................... 353
10.4.9 ITU Output Timing......................................................................................... 360
10.5 Interrupts ........................................................................................................................ 362
10.5.1 Setting of Status Flags .................................................................................... 362
10.5.2 Clearing of Status Flags.................................................................................. 364
10.5.3 Interrupt Sources and DMA Controller Activation ........................................ 365
10.6 Usage Notes .................................................................................................................... 366
Section 11 Programmable Timing Pattern Controller ......................................... 381
11.1 Overview ........................................................................................................................ 381
11.1.1 Features........................................................................................................... 381
11.1.2 Block Diagram................................................................................................ 382
11.1.3 TPC Pins ......................................................................................................... 383
11.1.4 Registers ......................................................................................................... 384
11.2 Register Descriptions...................................................................................................... 385
11.2.1 Port A Data Direction Register (PADDR) ...................................................... 385
11.2.2 Port A Data Register (PADR) ......................................................................... 385
11.2.3 Port B Data Direction Register (PBDDR) ...................................................... 386
11.2.4 Port B Data Register (PBDR) ......................................................................... 386
11.2.5 Next Data Register A (NDRA)....................................................................... 387
11.2.6 Next Data Register B (NDRB) ....................................................................... 389
11.2.7 Next Data Enable Register A (NDERA) ........................................................ 391
11.2.8 Next Data Enable Register B (NDERB)......................................................... 392
11.2.9 TPC Output Control Register (TPCR)............................................................ 393
11.2.10 TPC Output Mode Register (TPMR).............................................................. 396
11.3 Operation ........................................................................................................................ 398
11.3.1 Overview......................................................................................................... 398
11 Page | ||
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| PDF Descargar | [ Datasheet HD6413003TVF.PDF ] | |
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