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ISD2548 の電気的特性と機能

ISD2548のメーカーはISDです、この部品の機能は「(ISD2500 Series) Single-Chip Voice Record/Playback Devices」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISD2548
部品説明 (ISD2500 Series) Single-Chip Voice Record/Playback Devices
メーカ ISD
ロゴ ISD ロゴ 




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ISD2548 Datasheet, ISD2548 PDF,ピン配置, 機能
www.DataSheet4U.com
®
ISD2500 Series
Single-Chip Voice Record/Playback Devices
32-*, 40-*, 48-*, 64-*, 60-, 75-,
90-, and 120-Second Durations
FEATURES
• Easy-to-use single-chip voice Record/
Playback solution
• High-quality, natural voice/audio
reproduction
• Manual switch or microcontroller compati-
ble Playback can be edge- or level-
activated
• Single-chip durations of 32*, 40*, 48*, 64*,
60, 75, 90, and 120 seconds
• Directly cascadable for longer durations
• Automatic Power-Down (Push-Button
Mode)
– Standby current 1 µA (typical)
• Zero-power message storage
– Eliminates battery backup circuits
• Fully addressable to handle multiple
messages
• 100-year message retention (typical)
• 100,000 record cycles (typical)
• On-chip clock source
• No algorithm development required
• Single +5 volt power supply
• Available in die form, DIP, SOIC, and
TSOP packaging
• Industrial temperature (-40°C to +85°C)
versions available
1
ISD2500 SERIES SUMMARY
Part
Number
Duration
(Seconds)
ISD2560
ISD2575
ISD2590
ISD25120
ISD2532*
ISD2540*
ISD2548*
ISD2564*
60
75
90
120
32
40
48
64
Input Sample
Rate (KHz)
8.0
6.4
5.3
4.0
8.0
6.4
5.3
4.0
Typical Filter
Pass Band (KHz)
3.4
2.7
2.3
1.7
3.4
2.7
2.3
1.7
Information Storage Devices, Inc.
* Advance information: ISD2532/40/48/64 devices.
1–79

1 Page





ISD2548 pdf, ピン配列
Product Data Sheets
ISD2532/40/48/64* DEVICE BLOCK DIAGRAM
ISD2500 Series
XCLK
ANA IN
ANA OUT
MIC
MIC REF
AGC
Internal Clock
Timing
Sampling Clock
Amp
5-Pole Active
Antialiasing Filter
Pre-
Amp
Automatic
Gain Control
(AGC)
Analog Transceivers
256 K Cell
Nonvolatile
Multilevel Storage
Array
Power Conditioning
Address Buffers
R
5-Pole Active
Smoothing Filter
Mux Amp
Device Control
SP+
SP–
VCCA VSSA VSSD VCCD A0 A1 A2 A3 A4 A5 A6 A7 A8
PD OVF P/R CE EOM AUX IN
EEPROM Storage
One of the benefits of ISD’s ChipCorder technol-
ogy is the use of on-chip nonvolatile memory,
providing zero-power message storage. The mes-
sage is retained for up to 100 years typically
without power. In addition, the device can be re-
recorded typically over 100,000 times.
Microcontroller Interface
In addition to its simplicity and ease of use, the
ISD2500 Series includes all the interfaces neces-
sary for microcontroller-driven applications. The
address and control lines can be interfaced to a
microcontroller and manipulated to perform a vari-
ety of tasks, including message assembly,
message concatenation, predefined fixed mes-
sage segmentation, and message management.
Programming
The ISD2500 Series is also ideal for playback-only
applications, where single or multiple messages
are referenced through buttons, switches, or a
microcontroller. Once the desired message config-
uration is created, duplicates can easily be
generated via an ISD programmer.
PIN DESCRIPTIONS
Voltage Inputs (VCCA, VCCD)
To minimize noise, the analog and digital circuits in
the ISD2500 Series devices use separate power
busses. These voltage busses are brought out to
separate pins and should be tied together as close
to the supply as possible. In addition, these sup-
plies should be decoupled as close to the package
as possible.
Ground Inputs (VSSA, VSSD)
The ISD2500 Series of devices utilizes separate
analog and digital ground busses. These pins
should be connected separately through a low-
impedance path to power supply ground.
Power Down Input (PD)
When not recording or playing back, the PD pin
should be pulled HIGH to place the part in a very
low power mode (see ISB specification). When
OVF pulses LOW for an overflow condition, PD
should be brought HIGH to reset the address
pointer back to the beginning of the Record/Play-
back space. The PD pin has additional
functionality in the M6 (Push-Button) Operational
1
* Advance information: ISD2532/40/48/64 devices.
1–81


3Pages


ISD2548 電子部品, 半導体
ISD2500 Series
Product Data Sheets
specification. The frequency is then maintained to
a variation of ±2.25% over the entire commercial
temperature and operating voltage ranges. The
internal clock has a ±5% tolerance over the indus-
trial temperature and voltage range. A regulated
power supply is recommended for industrial tem-
perature range parts. If greater precision is
required, the device can be clocked through the
XCLK pin as follows:
Part
Number
-1
ISD2560
ISD2575
ISD2590
ISD25120
ISD2532*
ISD2540*
ISD2548*
ISD2564*
Sample Rate Required Clock
8.0 KHz
6.4 KHz
5.3 KHz
4.0 KHz
8.0 KHz
6.4 KHz
5.3 KHz
4.0 KHz
1024 KHz
819.2 KHz
682.7 KHz
512 KHz
1024 KHz
819.2 KHz
682.7 KHz
512 KHz
These recommended clock rates should not be
varied because the antialiasing and smoothing fil-
ters are fixed, and aliasing problems can occur if
the sample rate differs from the one recom-
mended. The duty cycle on the input clock is not
critical, as the clock is immediately divided by two.
IF THE XCLK IS NOT USED, THIS INPUT MUST BE CON-
NECTED TO GROUND.
Speaker Outputs (SP+/SP-)
All devices in the ISD2500 Series include an on-
chip differential speaker driver, capable of driving
50 milliwatts into 16 from AUX IN (12.2 mW from
memory).
The speaker outputs are held at VSSA levels during
record and power down. It is therefore not possible
to parallel speaker outputs of multiple ISD2500
devices or the outputs of other speaker drivers.
NOTE
Connection of speaker outputs in parallel
may cause damage to the device.
A single output may be used alone (including a
coupling capacitor between the SP pin and the
speaker). These outputs may be used individually
with the output signal taken from either pin. Using
the differential outputs results in a 4:1 improve-
ment in output power.
NOTE
Never ground or drive an unused speaker
output.
Auxiliary Input (AUX IN)
The Auxiliary Input is multiplexed through to the
output amplifier and speaker output pins when CE
is HIGH, P/R is HIGH, and Playback is currently
not active or if the device is in Playback overflow.
When cascading multiple ISD2500 devices, the
AUX IN pin is used to connect a Playback signal
from a following device to the previous output
speaker drivers. For noise considerations, it is sug-
gested that the auxiliary input not be driven when
the storage array is active.
Address/Mode Inputs (Ax/Mx)
The Address/Mode Inputs have two functions
depending on the level of the two Most Significant
Bits (MSB) of the address (A8 and A9 for the
ISD256075/90/120 devices, and A7 and A8 for the
ISD2532/40/48/64* devices).
If either or both of the two MSBs are LOW, the
inputs are ALL interpreted as address bits and are
used as the start address for the current Record or
Playback cycle. The address pins are inputs only
and do not output internal address information as
the operation progresses. Address inputs are
latched by the falling edge of CE.
If both MSBs are HIGH, the Address/Mode Inputs
are interpreted as Mode bits according to the
Operational Mode table on page 1-85. There are
six operational modes (M0..M6) available as indi-
1–84
* Advance information: ISD2532/40/48/64 devices.

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
ISD2540

SINGLE-CHIP/ MULTIPLE-MESSAGES/ VOICE RECORD/PLAYBACK DEVICE 32-/ 40-/ 48-/ AND 64-SECOND DURATION

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ISD2540

(ISD2500 Series) Single-Chip Voice Record/Playback Devices

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ISD2540E

SINGLE-CHIP/ MULTIPLE-MESSAGES/ VOICE RECORD/PLAYBACK DEVICE 32-/ 40-/ 48-/ AND 64-SECOND DURATION

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ISD2540P

SINGLE-CHIP/ MULTIPLE-MESSAGES/ VOICE RECORD/PLAYBACK DEVICE 32-/ 40-/ 48-/ AND 64-SECOND DURATION

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