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PDF AND8031D Data sheet ( Hoja de datos )
| Número de pieza | AND8031D | |
| Descripción | Isolated Precision Regulation of a Single 1.8 Volt Output from a Universal Line Input | |
| Fabricantes | ON Semiconductor | |
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AND8031/D
Isolated Precision
Regulation of a Single
1.8 Volt Output from a
Universal Line Input
Prepared by: Jason Hansen
ON Semiconductor
http://onsemi.com
APPLICATION NOTE
INTRODUCTION
The following Application Note describes an off–line
switching power supply utilizing a precision programmable
reference to regulate a 1.8 volt output. The center of the app
note is the MC33363B, a monolithic SMPS controller with
a 700 volt power switch, and the NCP100, a sub–one volt
precision programmable reference. The system design and
analysis will be described in detail.
The design requirements are for a universal off–line
converter with a 1.8 volt, 1.0 ampere single output with less
than 50 millivolts ripple and operates at 100 kHz. Most of the
components selected are surface mount. This design is
separated into the generic circuit of the off–line converter
and the feedback network.
Generic Off–Line Conversion Circuit
To reduce the total number of components and thus
minimize circuit board area, an SMPS controller with an
integrated power switch is selected. With the low output
power requirement, the MC33363B is selected as the control
and power switch IC. The MC33363B contains an externally
programmable frequency and current limit, internal startup
circuit and can handle up to 8 watts of output power.
The basic off–line conversion circuit is illustrated in
Figure 1. The line input is filtered through the EMC circuit
then rectified and filtered. The rectified voltage is converted
to a lower voltage via the transformer and the MC33363B.
The secondary of the transformer is rectified to a DC voltage
and filtered. The output voltage controls the duty cycle of the
switcher via the isolated feedback network. The calculated
values are a starting point and do not replace bench testing.
Universal
Input
R1
4.7
C1
1n
R2
4.7
D1
D2
4.7 µ
D3 400 V
D4
1N4005
R4 C5
3.9 k 47 p
C6
10 µ
U1
1 16
U2 CTX22–14966
D5
MURS160
D7
MBRD835L
D6
MURS120
C7 C8
820 µ 820 µ
Q1
BC858ALT1
R12
120
+
C12
1µ
1.8 V
–
C9
0.1 µ
R9
12 k
3
4 13
5
R3 30 k
6
C3 390 p
7
C4 1 µ
8
12
11
10
9
MC33363B
C10
1µ
R11
10
U4
NCP100 R10
7.5 k
R6
2.7 k
U3
SFH615–4
Figure 1. MC33363B Basic Flyback Circuit Schematic
© Semiconductor Components Industries, LLC, 2000
October, 2000 – Rev. 1
1
Publication Order Number:
AND8031/D
1 page  
AND8031/D
60
50 Gain
180
90
40
Phase
30
0
–90
20 –180
10
10
100 1 k 10 k
Frequency (Hz)
100 k
Figure 10. NCP100 with PNP
0
–10
–20
–30
–40
10
Gain
Phase
180
90
0
–90
–180
100 1 k 10 k
Frequency (Hz)
Figure 11. NCP100 without PNP
100 k
The values for the components in Figure 7 are as follows.
Rosc = 12 Ohms, R1 = 12 k Ohms, R2 is adjustable
dependant upon U1, R3 and R4 = 100 Ohms, C2 = 0.01 uF,
and C3 = 1.0 uF.
The open loop gain and phase test injects the oscillator
signal across Rosc. The reference voltage is measured
between Rosc and R1 to ground. The test voltage is
measured at the collector of Q1 for the PNP circuit or at the
cathode of U1 for the traditional circuit. Vout is set to 4.0
volts and R2 is adjusted so the DC test voltage is at the center
of its range. R2 is the only component adjusted since it is
neglected for AC analysis.
There are negligible differences for the open loop gain and
phase of the NCP100 with C3 compared to the TLV431
without C3 in the PNP circuit. Therefore there is no penalty
with the added C3 in the NCP100 circuit.
If the PNP transistor is removed, the TLV431 open loop
responses with and without C3 are very similar with a single
pole roll–off. The pole appears to be near 4 Hz.
The NCP100 without the PNP has flat gain until a pole at
1.3 kHz due to R1 and C2. The plot remains at
–20 dB/decade and –90 degree phase margin until well
beyond 100 kHz.
The overall gain of the feedback network can be limited
due to R1, R3 and C2 in Figure 7 . Varying these components
will modify the maximum gain of the system.
Since the NCP100 provides a single pole roll–off, the
MC33363B compensation pin will not provide this function.
The feedback pin of the MC33363B is connected directly to
the reference pin. This will keep the output of the error amp
low. A diode is in series with the output of the op–amp
allowing the compensation pin to directly control the
feedback to the oscillator ramp. The compensation pin is
connected to the feedback pin via a 2.7 k Ohm resistor. The
collector of the optocoupler is also connected to the
compensation pin and the emitter is grounded. This
completes the design of the system. See Figure 14 for the
board layout of the schematic in Figure 1 and Table 1 for the
component values.
http://onsemi.com
5
5 Page 
Notes
AND8031/D
http://onsemi.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AND8031D.PDF ] | |
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