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U637256 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 U637256
部品説明 CapStore 32K x 8 nvSRAM
メーカ Simteh
ロゴ Simteh ロゴ 



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U637256 Datasheet, U637256 PDF,ピン配置, 機能
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U637256
CapStore 32K x 8 nvSRAM
Features
Description
‡ CMOS non volatile static RAM The U637256 has two separate
32768 x 8 bits
‡ 70 ns Access Time
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
‡ 35 ns Output Enable Access
mode, the memory operates as an
Time
‡ ICC = 15 mA typ. at 200 ns Cycle
Time
‡ Unlimited Read and Write Cycles
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
to SRAM
mode SRAM functions are disab-
‡ Automatic STORE to EEPROM led.
on Power Down using charge
The U637256 is a static RAM with
stored in an integrated capacitor a nonvolatile electrically erasable
‡ Software initiated STORE
‡ Automatic STORE Timing
‡ 106 STORE cycles to EEPROM
PROM (EEPROM) element incor-
porated in each static memory cell.
The SRAM can be read and written
‡ 100 years data retention in
an unlimited number of times, while
EEPROM
independent nonvolatile data resi-
‡ Automatic RECALL on Power Up des in EEPROM. Data transfers
‡ Software RECALL Initiation
‡ Unlimited RECALL cycles from
from the SRAM to the EEPROM
(the STORE operation) take place
EEPROM
automatically upon power down
‡ Single 5 V ± 10 % Operation
‡ Operating temperature range:
using charge stored in an integraed
capacitor. Transfers from the
0 to 70 °C
EEPROM to the SRAM (the
-40 to 85°C
‡ QS 9000 Quality Standard
RECALL operation) take place
automatically on power up. The
(MIL STD 883C M3015.7)
U637256 combines the ease of use
‡ RoHS compliance and Pb- free of an SRAM with nonvolatile data
Package: PDIP28 (600 mil)
integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U637256 is pin compatible
with standard SRAMs and standard
battery backed SRAMs.
Pin Configuration
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 PDIP 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
March 31, 2006
STK Control #ML0054
Pin Description
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
1 Rev 1.0

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部品番号部品説明メーカ
U637256

CapStore 32K x 8 nvSRAM

Simteh
Simteh

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