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U63716 PDF Data sheet ( 特性 )

部品番号 U63716
部品説明 CAPSTORE 2K X 8 NVSRAM
メーカ ZMD
ロゴ ZMD ロゴ 



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U63716 Datasheet, U63716 PDF,ピン配置, 機能
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U63716
CapStore 2K x 8 nvSRAM
Features
Description
S CMOS non- volatile static RAM
2048 x 8 bits
S 70 ns Access Time
S 35 ns Output Enable Access Time
S ICC = 15 mA at 200 ns Cycle Time
S Unlimited Read and Write Cycles
to SRAM
S Automatic STORE to EEPROM
on Power Down using charge
stored in an integrated capacitor
S Software initiated STORE
S Automatic STORE Timing
S 106 STORE cycles to EEPROM
S 100 years data retention in
EEPROM
S Automatic RECALL on Power Up
S Software RECALL Initiation
S Unlimited RECALL cycles from
EEPROM
S Single 5 V ± 10 % Operation
S Operating temperature range:
0 to 70 °C
-40 to 85 °C
S QS 9000 Quality Standard
S ESD protection > 2000 V
(MIL STD 883C M3015.7)
S RoHS compliance and Pb- free
S Package: PDIP24 (600 mil)
The U63716 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In non-volatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U63716 is a static RAM with a
non-volatile electrically erasable
PROM (EEPROM) element incor-
porated in each static memory cell.
The SRAM can be read and written
an unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an integra-
ted capacitor. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
automatically on power up. The
U63716 combines the ease of use
of an SRAM with nonvolatile data
integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U63716 is pin compatible with
standard SRAMs and standard bat-
tery backed SRAMs.
Pin Configuration
Pin Description
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6 PDIP
7 24
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
April 7, 2005
1

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