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M1025 の電気的特性と機能

M1025のメーカーはICSTです、この部品の機能は「(M1025 / M1026) VCSO BASED CLOCK PLL」です。


製品の詳細 ( Datasheet PDF )

部品番号 M1025
部品説明 (M1025 / M1026) VCSO BASED CLOCK PLL
メーカ ICST
ロゴ ICST ロゴ 




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M1025 Datasheet, M1025 PDF,ピン配置, 機能
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
Product Data Sheet
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M1025/26 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1025/26 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
MR_SEL2
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30
31
M1025
32 M 1 0 2 6
16
15
14
33
34 ( T o p V i e w )
13
12
35 11
36 10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
FEATURES
Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Hitless Switching (HS) options with or without Phase
Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
Pin-selectable feedback and reference divider ratios
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M1025-11-155.5200 or M1026-11-155.5200
Input Reference
Clock (MHz)
(M1025)
(M1026)
19.44 or 38.88
77.76
155.52
622.08
PLL Ratio
(Pin Selectable)
(M1025) (M1026)
8 or 4
2
1
0.25
Output Clock
(MHz)
(Pin Selectable)
155.52
or
77.76
Table 1: Example I/O Clock Frequency Combinations
M1025/26
Loop Filter
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
4
MR_SEL3:0
MUX
0 R Div
1
PLL
Phase
Detector
0
1
Auto
Ref Sel
LOL
Phase
Detector
M/R Divider
LUT
M Divider
VCSO
P Divider
(1, 2, or TriState)
TriState
LOL
FOUT
nFOUT
2
P_SEL1:0
P Divider
LUT
Figure 2: Simplified Block Diagram
M1025/26 Datasheet Rev 1.0
Revised 28Jul2004
M1025/26 VCSO Based Clock PLL with AutoSwitch
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

1 Page





M1025 pdf, ピン配列
Integrated
Circuit
Systems, Inc.
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
DETAILED BLOCK DIAGRAM
M1025/26
OP_IN
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
4
MR_SEL3:0
MUX
0
1
R Div
PLL
Phase
Detector
RIN
R IN
0
1
Auto
Ref Sel
LOL
Phase
Detector
M / R Divider
LUT
RLOOP CLOOP
RLOOP CLOOP
nOP_IN
OP_OUT
Loop Filter
A m plifie r
M Divider
RPOST
R POST
CPOST
CPOST
nOP_OUT nVC
External
Loop Filter
Components
VC
Hitless Switching (HS) Opt.
HS with Phase Build-out Opt.
Phase
Locked
Loop
(PLL)
SAW Delay Line
Phase
Shifter
VCSO
P Divider
(1, 2, or TriState)
TriState
2
P_SEL1:0
P Divider
LUT
LOL
FOUT
nFOUT
DIVIDER SELECTION TABLES
Figure 3: Detailed Block Diagram
M and R Divider Look-Up Tables (LUT)
The MR_SEL3:0 pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up tables vary
by device variant. M1025 and M1026 are defined in
Tables 3 and 4 respectively.
M1025 M/R Divider LUT
Total
MR_SEL3:0 M Div R Div PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
0000 8 1
8
19.44
19.44
0 0 0 1 32 4
8
19.44
4.86
0 0 1 0 128 16 8
19.44
1.215
0 0 1 1 512 64 8
19.44
0.30375
0100 2 1
2
77.76
77.76
0101 8 4
2
77.76
19.44
0 1 1 0 32 16 2
77.76
4.86
0 1 1 1 128 64 2
77.76
1.215
1000 1 1
1
155.52
155.52
1001 4 4
1
155.52
38.88
1 0 1 0 16 16 1
155.52
9.72
1 0 1 1 64 64 1
1 1 0 0 Test Mode1 N/A
155.52
N/A
2.43
N/A
1101 1
4 0.25
622.08
155.52
1 1 1 0 4 16 0.25
622.08
38.88
1 1 1 1 16 64 0.25
622.08
9.72
Table 3: M1025 M/R Divider LUT
Note 1: Factory test mode; do not use.
ables 3 and 4 provide example Fin and phase
detector frequencies with 155.52MHz VCSO
devices (M1025-11-155.5200 and M1026-11-155.5200).
See “Ordering Information” on pg. 14.
M1026 M/R Divider LUT
Total
MR_SEL3:0 M Div R Div PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
0000 4 1
4
38.88
38.88
0 0 0 1 16 4
4
38.88
9.72
0 0 1 0 64 16
4
38.88
2.43
0 0 1 1 256 64
4
38.88
0.6075
0100 2 1
2
77.76
77.76
0101 8 4
2
77.76
19.44
0 1 1 0 32 16
2
77.76
4.86
0 1 1 1 128 64
2
77.76
1.215
1000 1 1
1
155.52
155.52
1001 4 4
1
155.52
38.88
1 0 1 0 16 16
1
155.52
9.72
1 0 1 1 64 64
1
1 1 0 0 Test Mode1 N/A
155.52
N/A
2.43
N/A
1 1 0 1 1 4 0.25 622.08
155.52
1 1 1 0 4 16 0.25 622.08
38.88
1 1 1 1 16 64 0.25 622.08
9.72
Table 4: M1026 M/R Divider LUT
Note 1: Factory test mode; do not use.
M1025/26 Datasheet Rev 1.0
3 of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400


3Pages


M1025 電子部品, 半導体
Integrated
Circuit
Systems, Inc.
TriState
The TriState feature puts the LVPECL output driver into
a high impedance state, effectively disconnecting the
driver from the FOUT and nFOUT pins of the device. A
logic 0 is then present on the clock net. The impedance
of the clock net is then set to 50by the external circuit
resistors. (This is in distinction to a CMOS output in
TriState, in which case the net goes to a high
impedance and the logic value floats.) The 50
impedance level of the LVPECL TriState allows
manufacturing In-circuit Test to drive the clock net with
an external 50generator to validate the integrity of
clock net and the clock load.
Any unused output (single-ended or differential) should
be left unconnected (floating) in system application.
This minimizes output switching current and therefore
minimizes noise modulation of the VCSO.
Loss of Lock Indicator (LOL) Output Pin
Under normal device operation, when the PLL is locked,
the LOL Phase Detector drives LOL to logic 0. Under
circumstances when the VCSO cannot lock to the input
(as measured by a greater than 4 ns discrepancy
between the feedback and reference clock rising edges
at the LOL Phase Detector) the LOL output goes to logic
1. The LOL pin will return back to logic 0 when the phase
detector error is less than 2 ns. The loss of lock
indicator is a low current LVCMOS output.
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Product Data Sheet
Guidelines Using LOL
As described, the LOL pin indicates when the PLL is
out-of-lock with the input reference. The LOL condition
is also used by the AutoSwitch circuit to detect a lost
reference, as described in following sections. LOL is
also used by the Hitless Switching and Phase Build-out
functions (optional device features).
To ensure reliable operation of LOL and guard against
false out-of-lock indications, the following conditions
should be met:
The phase detector frequency should be no less than
5MHz, and preferably it should be 10MHz or greater.
Phase detector frequency is defined by Fin / R.
A higher phase detector frequency will result in lower
phase error and less chance of false triggering the
LOL phase detector. Refer to Tables 3 and 4 on pg. 3
for phase detector frequency when using the
M1025-11-155.5200 or the M1026-11-155.5200.
The input reference should have an intrinsic jitter of
less than 1 ns pk-pk. If reference jitter is greater than
1 ns pk-pk, the LOL circuit might falsely trigger. Due
to this limitation, the LOL circuit should not be used in
loop timing mode, nor should it be used with a noisy
reference clock. Likewise, the AutoSwitch, Hitless
Switching, or Phase Build-out features should not be
used in loop timing mode or with a noisy reference
clock, since these features depend on LOL.
Reference Acknowledgement (REF_ACK) Output
The REF_ACK (reference acknowledgement) pin outputs
the value of the reference clock input that is routed to
the phase detector. Logic 1 indicates input pair 1
(nDIF_REF1, DIF_REF1); logic 0 indicates input pair 0
(nDIF_REF0, DIF_REF0). The REF_ACK indicator is an
LVCMOS output.
M1025/26 Datasheet Rev 1.0
6 of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

6 Page



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