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PDF LC78622NE Data sheet ( Hoja de datos )
| Número de pieza | LC78622NE | |
| Descripción | Compact Disc Player DSP | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : EN6015
CMOS IC
LC78622NE
Compact Disc Player DSP
Overview
The LC78622NE is a CMOS IC that implements the
signal processing and servo control required by compact
disc players. At the same time as providing an EFM PLL
circuit, a 1-bit D/A converter, and an analog low-pass
filter the LC78622NE realizes an optimal cost-
performance tradeoff for low-end players by strictly
limiting functionality to basic signal-processing and servo
system functionality. The LC78622NE signal-processing
system provides demodulation of the EFM signal from the
pickup, de-interleaving, error detection and correction, and
digital filters that can prove useful in reducing the cost of
end products. The LC78622NE servo control system
processes servo commands sent from the control
microprocessor.
The LC78622NE is an improved version of the LC78622E
that adds 8× oversampling digital filters, three general-
purpose output ports (that also have specific shared
functions) and the PCCL pin (pin 34). However, some
handling of general-purpose ports differ from that of the
LC78622E, therefore care must be taken.(Refer to pages
16 and 21).
Functions
• Input signal processing: The LC78622NE takes an HF
signal as input, digitizes (slices) that signal at a precise
level, converts that signal to an EFM signal, and
generates a PLL clock with an average frequency of
4.3218 MHz by comparing the phases of that signal and
an internal VCO.
• Precise reference clock and necessary internal timing
generation using an external 16.9344 MHz crystal
oscillator
• Disk motor speed control using a frame phase difference
signal generated from the playback clock and the
reference clock
• Frame synchronization signal detection, protection and
interpolation to assure stable data readout
• EFM signal demodulation and conversion to 8-bit
symbol data
• Subcode data separation from the EFM demodulated
signal and output of that data to an external
microprocessor
• Subcode Q signal output to a microprocessor over the
serial I/O interface after performing a CRC error check
(LSB first)
• Demodulated EFM signal buffering in internal RAM to
handle up to ±4 frames of disk rotational jitter
• Demodulated EFM signal reordering in the prescribed
order for data unscrambling and de-interleaving
• Error detection, correction, and flag processing (error
correction scheme: dual C1 plus dual C2 correction)
• Sets the C2 flags based on the C1 flags and a C2 check,
and then performs signal interpolation or muting
depending on the C2 flags. The interpolation circuit uses
a dual-interpolation scheme. The previous value is held
if the C2 flags indicate errors two or more times
consecutively.
• Support for command input from a control
microprocessor: commands include track jump, focus
start, disk motor start/stop, muting on/off and track
count (8 bit serial input)
• Built-in digital output circuits.
• Arbitrary track counting to support high-speed data
access
• D/A converter outputs with data continuity improved by
8× oversampling digital filters.
• Built-in third-order ∑∆ D/A converters (An analog low-
pass filter is built in.)
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
11999RM (OT) No. 6015-1/31
1 page  
LC78622NE
One-Bit D/A Converter Analog Characteristics
at Ta = 25°C, VDD = LVDD = RVDD = 5 V, VSS = LVSS = RVSS = 0 V
Parameter
Total harmonic distortion
Dynamic range
Signal-to-noise ratio
Crosstalk
Symbol
THD + N
DR
S/N
CT
Conditions
LCHO, RCHO; 1 kHz: 0 dB data input,
using the 20 kHz low-pass filter (AD725D built in)
LCHO, RCHO; 1 kHz: –60 dB data input,
using the 20 kHz low-pass filter and the A filter
(AD725D built in)
LCHO, RCHO; 1 kHz: 0 dB data input,
using the 20 kHz low-pass filter and the A filter
(AD725D built in)
LCHO, RCHO; 1 kHz: 0 dB data input,
using the 20 kHz low-pass filter (AD725D built in)
min typ max Unit
0.009
0.012
%
87 90
dB
93 95
82 84
dB
dB
Note: Measured with the normal-speed playback mode in the Sanyo one-bit D/A converter block reference digital attenuator circuit set to EE (hexadecimal).
Figure 1 Command Input
No. 6015-5/31
5 Page 
LC78622NE
• CLV mode
In CLV mode the LC78622NE detects the disk speed from the HF signal and provides proper linear speed using
several different control schemes by switching the DSP internal modes. The PWM reference period corresponds to
a frequency of 7.35 kHz. The V/P pin outputs a high level during rough servo and a low level during phase control.
Internal mode
Rough servo (velocity too low)
Rough servo (velocity too high)
Phase control (PCK locked)
CLV+
High
Low
PWM
CLV–
Low
High
PWM
V/P
High
High
Low
• Rough servo gain switching
MSB
LSB
10101000
10101001
Command
DISC 8 SET
DISC 12 SET
RES = low
q
For 8 cm disks, the rough servo mode CLV control gain can be set about 8.5 dB lower than the gain used for 12 cm
disks.
• Phase control gain switching
MSB
LSB
10110001
10110010
10110011
10110000
Command
CLV PHASE COMPARATOR DIVISOR: 1/2
CLV PHASE COMPARATOR DIVISOR: 1/4
CLV PHASE COMPARATOR DIVISOR: 1/8
NO CLV PHASE COMPARATOR DIVISOR USED
RES= low
q
The phase control gain can be changed by changing the divisor used by the dividers in the stage immediately
preceding the phase comparator.
No. 6015-11/31
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LC78622NE.PDF ] | |
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