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ISL3685 の電気的特性と機能

ISL3685のメーカーはIntersil Corporationです、この部品の機能は「RF/IF Converter and Synthesizer」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL3685
部品説明 RF/IF Converter and Synthesizer
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL3685 Datasheet, ISL3685 PDF,ピン配置, 機能
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TM
Data Sheet
ISL3685
January 2001 File Number 4860.2
2.4GHz RF/IF Converter and Synthesizer
The ISL3685 is a monolithic SiGe
half duplex RF/IF transceiver
designed to operate in the 2.4GHz
ISM band. The receive chain features
a low noise, gain selectable amplifier (LNA) followed by a
down-converter mixer. An up-converter mixer and a high
performance preamplifier compose the transmit chain. The
remaining circuitry comprises a high frequency Phase
Locked Loop (PLL) synthesizer with a three wire
programmable interface for local oscillator applications.
A reduced filter count is realized by multiplexing the receive
and transmit IF paths and by sharing a common differential
matching network. Furthermore, both transmit and receive
RF amplifiers can be directly connected to mixers as
bandwidth characteristics attenuate image frequencies. The
inherent image rejection of both the transmit and receive
functions allows this economic advantage.
The ISL3685 is housed in a 44 lead MLFP package well
suited for PCMCIA board and MINI PCI applications.
Ordering Information
PART NUMBER
ISL3685IR
ISL3685IR96
TEMP RANGE
(oC)
PACKAGE PKG. NO
-40 to 85 44 Ld MLFP L44.7x7
-40 to 85 Tape and Reel
Simplified Block Diagram
RX_IN
CP_DO
INTERFACE
REF_IN
TXA_OUT
PLL
MODULE
RX_MX_OUT
LO_IN
TX_MX_IN
Features
• Highly Integrated
• Multiplexed RX/TX IF Path prescribes Single IF Filter
• Programmable Synthesizer
• Gain Selectable LNA
• Power Management/Standby Mode
• Single Supply 2.7V to 3.3V Operation
Cascaded LNA/Mixer (High Gain)
• Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25dB
• SSB Noise Figure. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7dB
• Input IP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -12dBm
• IF Frequency . . . . . . . . . . . . . . . . . . . 280MHz to 600MHz
Cascaded LNA/Mixer (Low Gain)
• Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9dB
• Input P1dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5dBm
• IF Frequency . . . . . . . . . . . . . . . . . . . 280MHz to 600MHz
Cascaded Mixer/Preamplifier
• Transmit Cascaded Mixer/Preamplifier Gain . . . . . . .25dB
• SSB Noise Figure. . . . . . . . . . . . . . . . . . . . . . . . . . . .10dB
• Output P1dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4dBm
• IF Frequency . . . . . . . . . . . . . . . . . . . 280MHz to 600MHz
Applications
• IEEE802.11 1Mbps and 2Mbps Standard
• Systems Targeting IEEE802.11, 11Mbps Standard
• Wireless Local Area Networks
• PCMCIA Wireless Transceivers
• ISM Systems
• TDMA Packet Protocol Radios
• MINI PCI Wireless Transceivers
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2000
PRISM® is a registered trademark of Intersil Americas Inc. PRISM and design is a trademark of Intersil Americas Inc.

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ISL3685 pdf, ピン配列
ISL3685
Pin Description (Continued)
PIN NAME
DESCRIPTION
19
REF_IN
Synthesizer Reference Frequency Input, internally DC coupled and requires an external AC coupling capacitor.
20 SYN_VCC2 Synthesizer Positive Power Supply.
21 CP_VCC2 Synthesizer Charge Pump Positive Power Supply.
22
CP_DO
Synthesizer Charge Pump Output, feeds the PLL loop filter.
23 TX_MX_VCC1 Transmit Mixer Positive Power Supply.
24 TX_MX_OUT Transmit Mixer RF output, internal AC coupled and internally matched to 50Ω.
25 TX_MX_VCC1 Transmit Mixer Positive Power Supply.
26 TX_LO_Driver_ Transmit LO Driver Positive Power Supply.
VCC1
27
LO_IN+
Local Oscillator Positive Input, internally AC coupled, internally matched to 50when the LO is driven single ended
and the LO_IN- is grounded.
28
LO_IN-
Local Oscillator Negative Input, internally AC coupled, differential or single ended capability, ground externally for single
ended operation.
29 LO_VCC1 LO Buffer Positive Power Supply.
30 RX_LO_DRIVER Receiver LO Driver Positive Power Supply.
_VCC1
32 TX_MX_IN- Transmit Mixer Negative Input, internally DC coupled, high impedance input. Designed to share a common IF matching
network/IF SAW filter with the receive mixer. Care should be exercised regarding the PC board layout to avoid
interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing
the bandwidth of the IF matching network.
33 RX_MX_OUT- Receive Mixer Negative Output, open collector, high impedance output. Designed to share a common IF matching
network/IF SAW filter with the transmit mixer. Care should be exercised regarding the PC board layout to avoid
interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing
the bandwidth of the IF matching network.
34 RX_MX_OUT+ Receive Mixer Positive Output, open collector, high impedance output. Designed to share a common IF matching
network/IF SAW filter with the transmit mixer. Care should be exercised regarding the PC board layout to avoid
interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing
the bandwidth of the IF matching network.
35 TX_MX_IN+ Transmit Mixer Positive Input, internally DC coupled, high impedance input. Designed to share a common IF matching
network/IF SAW filter with the receive mixer. Care should be exercised regarding the PC board layout to avoid
interference and noise pickup. Layout symmetry and management of PC board parasitics is also critical for maximizing
the bandwidth of the IF matching network.
36 RX_MX_IN Receive Mixer RF Input, internally DC coupled and requires external AC coupling as well as RF matching. The
recommend network consists of a 3.3pF series capacitor followed by a small series inductance of 1.4nH and then a
1.2nH shunt inductor. The series inductance is best implemented on the PC board using a narrow transmission line
inductor.
37 PRE_VCC1 PLL Prescaler Positive Power Supply.
38 ITAT_RES1 Connection to external resistor sets the receive and transmit mixers tail currents, independent of Absolute Temperature.
39 PTAT_RES Connection to external resistor sets the receive and transmit mixers tail currents, proportional of Absolute Temperature.
40 BIAS2_VCC1 Bias Positive Power Supply for the receive and transmit mixers.
41 ITAT_RES2 Connection to external resistor sets the LNA and Preamplifier bias currents, independent of Absolute Temperature.
42
RF_OUT
Low Noise Amplifier RF Output, internally AC coupled and internally matched to 50Ω.
44 COL_OUT LNA Collector Output, requires a bypass capacitance which is resonant with the PC board parasitics. A small resistance
(20Ω) in series with the main PC board VCC bus is recommended to provide isolation from other VCC bypass
capacitors. This ensures the image rejection performance of the LNA is maintained.
All
Others
GND
Circuit Ground Pins (Quantity 6 each).
3


3Pages


ISL3685 電子部品, 半導体
ISL3685
Phase Lock Loop Electrical Specifications (See Notes 4 through 12) (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Reference Oscillator Sensitivity, CMOS Inputs, Single
Ended or Complementary
- CMOS - Note 7
Reference Oscillator Duty Cycle
CMOS Inputs
40 - 60 %
Charge Pump Sink/Source Current/Tolerance
250µA Selection ±25%
0.18 0.25 0.32 mA
Charge Pump Sink/Source Current/Tolerance
500µA Selection ±25%
0.375 0.50 0.625 mA
Charge Pump Sink/Source Current/Tolerance
750µA Selection ±25%
0.56 0.75 0.94 mA
Charge Pump Sink/Source Current/Tolerance
1mA Selection ±25%
0.75 1.0 1.25 mA
Charge Pump Sink/Source Mismatch
- - 15 %
Charge Pump Output Compliance
Charge Pump Supply Voltage
Charge Pump VCC = VCC2
0.5
2.7
-
VCC2 -0.5
V
- 3.6 V
Serial Interface Clock Width
High Level tCWH
20 -
- ns
Low Level tCWL
20 -
- ns
Serial Interface Data/Clk Set-Up Time tCS
20 -
- ns
Serial Interface Data/Clk Hold Time tCH
10 -
- ns
Serial Interface Clk/LE Set-Up Time tES
20 -
- ns
Serial Interface LE Pulse Width tEW
20 -
- ns
NOTES:
4. The Serial data is clocked on the Rising Edge of the serial clock, MSB first. The serial Interface is active when LE is LOW. The serial Data is
latched into defined registers on the rising edge of LE.
5. As long as power is applied, all register settings will remain stored, including the power down state. The system may then come in and out of
the power down state without requiring the registers to be rewritten.
6. CMOS Reference Oscillator input levels are given in the General Electrical Specification section.
POWER ENABLE TRUTH TABLE
PLL_PE
PE1 PE2 (SERIAL BUS)
STATUS
0 0 1 Power Down State, PLL in Save Mode, Active Serial Interface
1 1 1 Receive State
1 0 1 Transmit State
0 1 1 PLL Inactive, Inactive RX, TX, Active Serial Interface
X X 0 PLL Disabled, Disabled PLL Registers, Active Serial Interface
NOTE:
7. PLL_PE is controlled via the serial interface, and can be used to disable the synthesizer. The actual synthesizer control is a logic AND function
of PLL_PE and the result of the logic OR function of PE1 and PE2. PE1 and PE2 directly control the power enable functionality of the LO buffers.
PLL Synthesizer Table
REGISTER
DEFINITION
SERIAL BITS LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 MSB
R Counter
0 0 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) R(8) R(9) R(10) R(11) R(12) R(13) R(14) X (Don’t Care)
A/B Counter 0
1 A(0) A(1) A(2) A(3) A(4) A(5) A(6) B(0) B(1) B(2) B(3) B(4) B(5) B(6) B(7) B(8) B(9) B(10)
Operational 1 0 M(0) 0 M(2) M(3) M(4) M(5) M(6) M(7) M(8) 0 0 0 0 M(13) M(14) M(15) X X
Mode
6

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