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CS43L41 の電気的特性と機能

CS43L41のメーカーはCirrus Logicです、この部品の機能は「DAC」です。


製品の詳細 ( Datasheet PDF )

部品番号 CS43L41
部品説明 DAC
メーカ Cirrus Logic
ロゴ Cirrus Logic ロゴ 




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CS43L41 Datasheet, CS43L41 PDF,ピン配置, 機能
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CS43L41
Low Power 24-Bit, 96 kHz DAC with Volume Control
Features
l Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
l ATAPI Mixing
l 101 dB Dynamic Range
l 89 dBFS THD+N
l Low Clock Jitter Sensitivity
l +2.4 V to +5 V Power Supply
l Filtered Line Level Outputs
l On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
l Digital Volume Control with Soft Ramp
– 94 dB Attenuation
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
l 24 mW with 2.4 V supply
I
Description
The CS43L41 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera-
ture and a high tolerance to clock jitter.
The CS43L41 accepts data at audio sample rates from
2 kHz to 100 kHz, consumes very little power and oper-
ates over a wide power supply range. These features are
ideal for portable DVD, portable MP3, Mini-Disc, and
mobile phones.
ORDERING INFORMATION
CS43L41-KZ
16-pin TSSOP, -10 to 70 °C
SCL/CCLK SDA/CDIN AD0/CS
MUTEC
RST
SCLK
LRCK
SDATA
Control Port
Interpolation Filter
Interpolation Filter
External
Mute Control
Volume Control
∆Σ DAC
Analog Filter
AOUTA
Mixer
Volume Control
∆Σ DAC
Analog Filter
AOUTB
÷2
Advanced Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
MCLK
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 1999
(All Rights Reserved)
SEP ‘99
DS473PP1
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CS43L41 pdf, ピン配列
Confidential Draft
9/23/99
CS43L41
Positive Voltage Reference - FILT+........................................................................................ 22
Quiescent Voltage - VQ .......................................................................................................... 22
Master Clock - MCLK ............................................................................................................. 23
Left/Right Clock - LRCK ......................................................................................................... 23
Serial Audio Data - SDATA .................................................................................................... 23
Serial Clock - SCLK ................................................................................................................ 24
Reset - RST ............................................................................................................................ 24
Serial Control Interface Clock - SCL/CCLK ........................................................................... 24
Serial Control Data I/O - SDA/CDIN ....................................................................................... 24
Address Bit / Chip Select - AD0/CS........................................................................................ 24
Mute Control - MUTEC ........................................................................................................... 24
6. APPLICATIONS ..................................................................................................................... 25
6.1 Grounding and Power Supply Decoupling ....................................................................... 25
6.2 Oversampling Modes ....................................................................................................... 25
6.3 Recommended Power-up Sequence ............................................................................... 25
6.4 Use of the Power ON/OFF Quiescent Voltage Ramp ..................................................... 25
7. CONTROL PORT INTERFACE .............................................................................................. 26
7.1 SPI Mode ......................................................................................................................... 26
7.2 I2C Compatible Mode ...................................................................................................... 26
7.3 Memory Address Pointer (MAP) ....................................................................................... 27
8. PARAMETER DEFINITIONS .................................................................................................. 33
Total Harmonic Distortion + Noise (THD+N) .......................................................................... 33
Dynamic Range ...................................................................................................................... 33
Interchannel Isolation ............................................................................................................. 33
Interchannel Gain Mismatch ................................................................................................... 33
Gain Error ............................................................................................................................... 33
Gain Drift ................................................................................................................................ 33
9. REFERENCES ........................................................................................................................ 33
10. PACKAGE DIMENSIONS .................................................................................................... 34
DS473PP1
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3Pages


CS43L41 電子部品, 半導体
CS43L41
ANALOG CHARACTERISTICS (Continued)
Parameters
Analog Output
Full Scale Output Voltage
Quiescent Voltage
Interchannel Gain Mismatch
Gain Drift
AC-Load Resistance
Load Capacitance
Symbol Min Typ Max Units
VQ
(Note 2)
(Note 2)
RL
CL
0.63•VA
-
-
-
3
-
0.7•VA
0.5•VA
0.1
100
-
-
0.77•VA
-
-
-
-
100
Vpp
VDC
dB
ppm/°C
k
pF
Base-rate Mode
High-Rate Mode
Parameter
Symbol Min Typ
Max Min Typ Max Unit
Combined Digital and On-chip Analog Filter Response (Note 3)
Passband
(Note 4)
to -0.05 dB corner
to -0.1 dB corner
to -3 dB corner
0 - .4535 - - - Fs
--
- 0 - .4621 Fs
0 - .4998 0 - .4982 Fs
Frequency Response 10 Hz to 20 kHz
-.02 -
+.08 -0.06 -
0 dB
StopBand
.5465 -
- .577 -
- Fs
StopBand Attenuation
(Note 5)
50 -
- 55 -
- dB
Group Delay
tgd - 9/Fs - - 4/Fs - s
Passband Group Delay Deviation 0 - 40 kHz
0 - 20 kHz
--
- ±0.36/Fs
-
-
- ±1.39/Fs -
- ±0.23/Fs -
s
s
De-emphasis Error
(Relative to 1 kHz)
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
- - +.2/-.1
- - +.05/-.14
- - +0/-.22
(Note 6)
dB
dB
dB
Notes: 2. Refer to Figure 18.
3. Filter response is guaranteed by design.
4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9-16) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
5. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
6. De-emphasis is not available in High-Rate Mode.
6 DS473PP1

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共有リンク

Link :


部品番号部品説明メーカ
CS43L41

DAC

Cirrus Logic
Cirrus Logic
CS43L42

Stereo DAC

Cirrus Logic
Cirrus Logic
CS43L43

Stereo DAC

Cirrus Logic
Cirrus Logic


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