CN8330 Datasheet PDF - Conexant Systems
| Part Number | CN8330 | |
| Description | DS3/E3 Framer | |
| Manufacturers | Conexant Systems | |
| Logo |  |
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CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
The CN8330 is an integral DS3/E3 framer designed to support the transmission
formats defined by ANSI T1.107-1988, T1.107a-1989, T1.404, and ITU-T G.751
standards. All maintenance features required by Bellcore TR-TSY-000009 and AT&T
PUB 54014 are provided. In addition, the CN8330 can be optionally configured as a
High-Level Data Link Controller (HDLC) usable with or without DS3/E3 framing
overhead.
The CN8330 provides framing recovery for M13, C-bit parity, Syntran, and G.751
E3 formatted signals. A First In First Out (FIFO) buffer in the receive path can be
enabled to reduce jitter on the incoming data. Transmit and receive data is available to
the host in either serial or parallel byte and nibble formats. Access is provided to the
terminal data link and the Far End Alarm/Control (FEAC) channel, as specified in
T1.107a-1989. Counters are included for frame-bit errors, Line Code Violations
(LCVs), parity errors, and Far End Block Errors (FEBEs).
Two operational modes are available: microprocessor and stand-alone monitor
control modes. The microprocessor control mode monitors all status conditions and
provides configuration control. The stand-alone monitor mode allows the CN8330 to
operate as a monitor providing status and alarm information on external pins.
Distinguishing Features
• Supports DS3/E3 framing modes
• Includes high-speed HDLC controller
(52 MHz)
• Framing recovery for M13, C-bit
parity, Syntran, and G.751 E3 signals
• Serial or parallel (octet or nibble)
interface modes
• Average reframe time of less than
1 ms for DS3 and less than 250 µs
for E3
• Supports the LAPD terminal data link
and FEAC channel as defined in
T1.107a-1989
• 68-pin PLCC or 80-pin MQFP
surface-mount package
• Operates from a single +5 VDC ±5%
power supply
• Low-power CMOS technology
Functional Block Diagram
RXPOS
RXNEG
DS3CKI
TXCKI
M
U
X
Source
Loopback
Unipolar
Conversion
Bypass
FIFO
FIFO
Enable
Framing
Recovery
Overhead/
Data Link
Processing
RXMSY
CBITO
RXCCK
RXDAT
RXCLK
Status
Applications
• Digital PCM switches
• Digital Cross-Connect Systems
• Channel Service Units (CSUs)
• Channel extenders
• ATM Switches/Concentrators
• PBXs
• Switched Multimegabit Digital
Service (SMDS) Equipment
• Test equipment
• Routers (including HSSI ports)
TXPOS
TXNEG
TCLKO
PPDL
Receiver
RDAT[7:0]
RXBCK
M Status
U
X
Bipolar
Framing/
PPDL
TXBCK
Encoder
Overhead
Insertion
Transmitter
TDAT[7:0]
AD[7:0]
Control
Line
Loopback
Microprocessor
Interface
To/From
All Blocks
Overhead/
Data Link
Processing
TXCCK
CBITI
TXCKI
TXDATI
TXSYI
Data Sheet
100441E
October 13, 1999
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CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
4.0 Mechanical/Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2.1 Power Requirements and Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.3.1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.4 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Appendix A Multimegabit HDLC Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.2 Block and Logic Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A.3 PPDL Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
A.3.1 PPDL Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1 DS3CKI Clock Duty Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.2 Overhead Bit Insertion in E3 Parallel Payload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.3 HDLC Formatter Mode Support While Configured for E3 Framing . . . . . . . . . . . . . . . . . . . . . . . B-2
Appendix C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
100441E
Conexant
iii
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ CN8330.PDF Datasheet ] | |
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